SNOSDC1A June 2024 – October 2024 LMH1229 , LMH1239
PRODUCTION DATA
For general LMH12x9 design requirements, reference the guidelines in Table 7-2.
For cable equalizer with loop-through application-specific requirements, reference the guidelines in Table 7-3.
DESIGN PARAMETER | REQUIREMENTS |
---|---|
SDI_IN+, SDI_IN1+ (LMH1239 only), SDI_OUT+ AC-coupling capacitors | 4.7μF 0402 surface mount ceramic capacitors recommended. |
SDI_IO–, SDI_IN1– (LMH1239 only), SDI_OUT– AC-coupling capacitors | 4.7μF 0402 surface mount ceramic capacitors recommended, AC terminated with 75Ω to VSS. Negative polarity can be used if positive polarity is AC terminated with 75Ω to VSS. |
OUT0± and OUT1± AC-coupling capacitors | 4.7μF 0402 surface mount ceramic capacitors recommended. |
Input and output terminations | Input and output terminations provided internally. Do not add external terminations. |
High-speed OUT0± and OUT1± trace impedance | Route the OUT0± and OUT1± with coupled board traces and100Ω differential impedance. |
SMPTE return loss | Place BNC within 1 inch of the LMH12x9 and consult BNC vendor for recommended BNC landing pattern to meet SMPTE requirements. |
SDI_IN+ and SDI_OUT+ crosstalk | When a long length coax cable is connected to SDI_IN+,
the signal amplitude at SDI_IN+ can be just a few mVpp. Layout precautions must be
taken to minimize crosstalk from adjacent devices or from adjacent output port
SDI_OUT+. To reduce cross coupling effects, keep SDI_OUT+ traces as far from SDI_IN+
as possible. When SDI_OUT+ is not used, TI recommends to turn off the output
(SDI_OUT_SEL = H) for best results. Note: When using the LMH1239, the same design requirements are applicable for SDI_IN1+ and SDI_OUT+ too. |
DC power supply decoupling capacitors | 10μF and 1μF bulk capacitors: place close to each device. 0.1μF capacitor: place close to each supply pin. |
VDD_LDO decoupling capacitors | 1μF and 0.1μF capacitors: place as close as possible to the device VDD_LDO pin. Do not use VDD_LDO as a 1.8V power supply source to external components. |
MODE_SEL Pin | SPI: Leave MODE_SEL unconnected (Level F) SMBus: Connect 1kΩ to VSS (Level L) |
Input SDI Reclocked Data Rate | 11.88Gbps, 5.94Gbps, 2.97Gbps, 1.485Gbps, or Divide-by-1.001 sub-rates and 270Mbps. For all other input data rates, the reclocker is automatically bypassed. |
DESIGN PARAMETER | REQUIREMENTS |
---|---|
OUT_MUX_SEL Pin | 1kΩ to VSS (Level L) or float (Level F) to enable OUT0± only. 20kΩ to VSS (Level R) to enable both OUT0± and OUT1±. |
LOOP_BW_SEL Pin | 1kΩ to VIN (Level H) or float (Level F) for default CDR loop
bandwidth operation (no external capacitor on LF±). 20kΩ to VSS (Level R) or 1kΩ to VSS (Level L) for decreased loop bandwidth (external capacitor required on LF±). |
SDI_OUT_SEL Pin | 1 kΩ to VSS (Level L) to enable cable loop-through SDI_OUT. 1 kΩ to VIN (Level H) to disable cable loop-through SDI_OUT. |