IDD |
Total supply current |
Default register settings, no load on logic outputs. VDD = 3.465 V |
|
170 |
212 |
mA |
IDD |
Total supply current |
PLL2, PLL3 and PLL4 disabled, no load on logic outputs. VDD = 3.465 V |
|
60 |
100 |
mA |
REFERENCE INPUTS (Hin, Vin, Fin) |
VIL |
Low input voltage |
IIN = ±10 μA |
0 |
|
0.3 VDD |
V |
VIH |
High input voltage |
IIN = ±10 µA |
0.7 VDD |
|
VDD |
V |
TAFD |
Auto-format detection time |
Time from when reference input first presented to when detected as indicated by NO_REF going low. Reference timing must be stable and accurate (no missing pulses). |
|
2 |
4 |
Input Frames |
OSCin LOGIC INPUTS |
VIL |
Low input voltage |
IIN = ±10 µA |
0 |
|
0.3 VDD |
V |
VIH |
High input voltage |
IIN = ±10 µA |
0.7 VDD |
|
VDD |
V |
I2C INTERFACE (SDA, SCL) |
VIL |
Low input voltage |
|
0 |
|
0.3 VDD |
V |
VIH |
High input voltage |
|
0.7 VDD |
|
VDD |
V |
IIN |
Input current |
VIN between 0.1 VDD and 0.9 VDD |
−10 |
|
+10 |
μA |
IOL |
Low output sink current |
VOL = 0V or 0.4V |
|
1.25 |
|
mA |
STATUS FLAG OUTPUTS (NO_REF, NO_ALIGN,NO_LOCK) |
VOL |
Low output voltage |
IOUT = +10 mA |
|
|
0.4 |
V |
VOH |
High output voltage |
IOUT = −10 mA |
VDD-0.4V |
|
|
V |
FRAME TIMING OUTPUTS |
VOL |
Low output voltage |
IOUT = +10 mA Fout1, Fout2, Fout3(6) |
|
|
0.4 |
|
VOH |
High output voltage |
IOUT = -10mA Fout1, Fout2, Fout3(6) |
VDD-0.4 V |
|
|
|
IOZ |
Output shutdown leakage current |
Output buffer shutdown, pin connected to VDD or GND VDD = 3.465V |
|
0.4 |
10 |
|μA| |
VIDEO and AUDIO CLOCK OUTPUTS (CLKout1, CLKout2 and CLKout3) |
tDJ |
27 MHz TIE deterministic Jitter |
Measured at CLKout1 all other CLKouts shutdown |
|
250 |
|
fs |
Measured at CLKout1, other CLKouts output default PLL |
|
250 |
|
fs |
148.5 MHz TIE deterministic Jitter |
Measured at CLKout2 all other CLKouts shutdown |
|
8 |
|
ps |
Measured at CLKout2, other CLKouts output default PLL |
|
8 |
|
ps |
148.35 MHz TIE deterministic Jitter |
Measured at CLKout3 all other CLKouts shutdown |
|
4 |
|
ps |
Measured at CLKout3, other CLKouts output default PLL |
|
4 |
|
ps |
24.576 MHz TIE deterministic Jitter |
Measured at CLKout4 all other CLKouts shutdown |
|
15 |
|
ps |
Measured at CLKout4, other CLKouts output default PLL |
|
15 |
|
ps |
tRJ |
27 MHz TIE random Output Jitter(4) |
Measured at CLKout1, other CLKouts shutdown |
|
2.7 |
|
ps |
Measured at CLKout1, other CLKouts output default PLL |
|
2.7 |
|
ps |
148.5 MHz TIE Random Output Jitter(4) |
Measured at CLKout2, other CLKouts shutdown |
|
3.0 |
|
ps |
Measured at CLKout2, other CLKouts output default PLL |
|
3.0 |
|
ps |
148.35 MHz TIE Random Output Jitter (4) |
Measured at CLKout3, other CLKouts shutdown |
|
3.5 |
|
ps |
Measured at CLKout3, other CLKouts output default PLL |
|
3.5 |
|
ps |
24.576 MHz TIE Random Output Jitter(4) |
Measured at CLKout4, other CLKouts shutdown |
|
3.4 |
|
ps |
Measured at CLKout4, other CLKouts output default PLL |
|
3.4 |
|
ps |
TD |
Duty cycle |
Measured at 50% level of clock amplitude, any output clock |
|
50% |
|
|
tR |
Rise time 20% to 80% |
15 pF load |
|
400 |
|
ps |
tF |
Fall time 80% to 20% |
15 pF load |
|
400 |
|
ps |
VOD |
Differential signal output voltage |
100 Ω differential load, CLKout1, CLKout2 or CLKout3(7) |
247 |
350 |
454 |
mV |
VOS |
Common signal output voltage |
100 Ω differential load, CLKout1, CLKout2 or CLKout3(7) |
1.125 |
1.25 |
1.375 |
V |
|VOD| |
|Change to VOD| for complementary output states |
100 Ω differential load, CLKout1, CLKout2 or CLKout3(7) |
|
|
50 |
|mV| |
|VOS| |
|Change to VOS| for complementary output states |
100 Ω differential load, CLKout1, CLKout2 or CLKout3(7) |
|
|
50 |
|mV| |
IOS |
Output short circuit current |
Differential clock output pins connected to GND for CLKout1, CLKout2, or CLKout3 |
|
|
24 |
|mA| |
IOZ |
Output shutdown leakage current |
Output buffer in shutdown mode, differential clock output pins connected to VDD or GND |
|
1 |
10 |
|µA| |
VCXO INPUT (XOin) |
fOFF |
Maximum relative frequency offset between VCXO input and H input |
Assumes H input jitter of ±15 ns |
|
±150 |
|
ppm |
VXOin_SE |
Single-ended signal input voltage range |
Single-ended input buffer mode |
0 |
|
VDD |
V |
VXOin_DIFF |
Differential signal input voltage range |
Differential input buffer mode, VCM = 1.2 V |
247 |
350 |
454 |
mV |
DIGITAL HOLDOVER and FREE-RUN SPECIFICATIONS |
VVCout_RNG |
DAC output voltage range |
Digital Free-run Mode |
0.5 |
|
VDD - 0.5V |
V |