SBOSAF0A april   2023  – august 2023 LMH32401-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Gain = 2 kΩ
    6. 6.6 Electrical Characteristics: Gain = 20 kΩ
    7. 6.7 Electrical Characteristics: Both Gains
    8. 6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switched Gain Transimpedance Amplifier
      2. 7.3.2 Clamping and Input Protection
      3. 7.3.3 ESD Protection
      4. 7.3.4 Differential Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ambient Light Cancellation (ALC) Mode
      2. 7.4.2 Power-Down Mode (Multiplexer Mode)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Application Information

The differential outputs of the LMH32401-Q1 can directly drive a high-speed differential input ADC. Figure 8-1 shows the LMH32401-Q1 differential outputs directly driving the ADC12QJ1600. The effective signal gain between the TIA input and the ADC input is 2 kΩ or 20 kΩ when driving an ADC with a 100-Ω differential input impedance (RADC_IN = 50 Ω). Equation 2 gives the effective signal gain between the TIA input and the ADC input when driving an ADC with any other value of differential input impedance (RADC_IN ≠ 50 Ω).

GUID-20230418-SS0I-HCHG-PT8L-FKLSF59QM92Q-low.svg Figure 8-1 LMH32401-Q1 to ADC Interface
Equation 2. A Z = 2   k Ω   ( o r   20   k Ω ) × 1.2 × 2 × R A D C _ I N ( 2 × R A D C I N + 20   Ω )

where

  • AZ = Differential gain from the TIA input to the ADC input
  • RADC_IN = Input resistance of the ADC

Figure 8-2 shows a matching resistor network between the LMH32401-Q1 output and the ADC12QJ1600 input. The matching network is needed to prevent signal reflections when the signal path between the LMH32401-Q1 and ADC is very long. Equation 3 gives the effective gain from the TIA input to the ADC input when using a matching resistor network.

GUID-20230418-SS0I-7LT2-P9PM-R5H8MPF9QCBW-low.svg Figure 8-2 LMH32401-Q1 to ADC Interface With a Matching Resistor Network
Equation 3. A Z = 2   k Ω   ( o r   20   k Ω ) × 1.2 × 2 × R A D C _ I N ( 2 × R A D C _ I N + 2 × R I S O + 20   Ω )

where

  • AZ = Gain from the TIA input to the ADC input
  • RADC_IN = Differential input resistance of the ADC
  • RISO = Series resistance between the TIA and ADC

Equation 4 gives the voltage to be applied at VOD (pin 9) if a certain differential offset voltage (VOD) is needed at the ADC input for the circuit in Figure 8-2.

Equation 4. V V O D = V O D × 1 1.2 × ( 2 × R A D C _ I N + 2 × R I S O + 20   Ω ) ( 2 × R A D C _ I N )

where

  • VVOD = Voltage applied at pin 9
  • VOD = Desired differential offset voltage at the ADC input
  • RADC_IN = Differential input resistance of the ADC
  • RISO = Series resistance between the TIA and ADC