SBOS849B December   2017  – February 2019 LMH5401-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      LMH5401-SP Small Signal Frequency Response
      2.      LMH5401-SP Driving an ADC12D1620QML
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3.3 V
    7. 7.7 Typical Characteristics: 5 V
    8. 7.8 Typical Characteristics: 3.3 V
  8. 8 Parameter Measurement Information
    1. 8.1  Output Reference Nodes and Gain Nomenclature
    2. 8.2  ATE Testing and DC Measurements
    3. 8.3  Frequency Response
    4. 8.4  S-Parameters
    5. 8.5  Frequency Response with Capacitive Load
    6. 8.6  Distortion
    7. 8.7  Noise Figure
    8. 8.8  Pulse Response, Slew Rate, and Overdrive Recovery
    9. 8.9  Power Down
    10. 8.10 VCM Frequency Response
    11. 8.11 Test Schematics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully-Differential Amplifier
      2. 9.3.2 Operations for Single-Ended to Differential Signals
        1. 9.3.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.3.2.2 DC-Coupled Input Signal Path Considerations for SE-DE Conversions
        3. 9.3.2.3 Resistor Design Equations for Single-to-Differential Applications
        4. 9.3.2.4 Input Impedance Calculations
      3. 9.3.3 Differential-to-Differential Signals
        1. 9.3.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.3.3.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      4. 9.3.4 Output Common-Mode Voltage
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation With a Split Supply
      2. 9.4.2 Operation With a Single Supply
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Stability, Noise Gain, and Signal Gain
      2. 10.1.2 Input and Output Headroom Considerations
      3. 10.1.3 Noise Analysis
      4. 10.1.4 Noise Figure
      5. 10.1.5 Thermal Considerations
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Driving Matched Loads
        2. 10.2.2.2 Driving Unmatched Loads For Lower Loss
        3. 10.2.2.3 Driving Capacitive Loads
        4. 10.2.2.4 Driving ADCs
          1. 10.2.2.4.1 SNR Considerations
          2. 10.2.2.4.2 SFDR Considerations
          3. 10.2.2.4.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
          4. 10.2.2.4.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
        5. 10.2.2.5 GSPS ADC Driver
        6. 10.2.2.6 Common-Mode Voltage Correction
        7. 10.2.2.7 Active Balun
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Do:
      2. 10.3.2 Don't:
  11. 11Power Supply Recommendations
    1. 11.1 Supply Voltage
    2. 11.2 Single Supply
    3. 11.3 Split Supply
    4. 11.4 Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics: VS = 3.3 V

The specifications shown below correspond to the respectively identified subgroup temperature (see Table 1), unless otherwise noted. VS+ = 3.3 V; VS– = 0 V; VCM = 1.65 V; RLtotal = 200-Ω differential(2); Gp = 8 dB (Gv = 17 dB); single-ended input, differential output, and input and output referenced to midsupply (unless otherwise noted); measured using an EVM as discussed in the Parameter Measurement Information section.
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
AC PERFORMANCE
GBP Gain bandwidth product Gp = 8 dB 6.5 GHz
SSBW Small-signal, –3-dB bandwidth VL = 100 mVPP 4 GHz
LSBW Large-signal, –3-dB bandwidth VL = 1 VPP 3.8 GHz
Bandwidth for ±0.5-dB flatness VL = 1 VPP 2.6 GHz
SR Slew rate 2-V step 17500 V/µs
Rise and fall time 1-V step, 10% to 90% 90 ps
Overdrive recovery Overdrive = ±0.5 V 400 ps
Output balance error f = 1 GHz –47 dBc
zo Output impedance At dc [1, 2, 3] 13 20 25 Ω
0.1% settling time 2 V, RL = 200 Ω 1 ns
HD2 Second-order harmonic distortion f = 100 MHz, VL = 500 mVPP –93 dBc
f = 200 MHz, VL = 500 mVPP –87
f = 500 MHz, VL = 500 mVPP –75.2
f = 1 GHz, VL = 500 mVPP –58
HD3 Third-order harmonic distortion f = 100 MHz, VL = 500 m VPP –83 dBc
f = 200 MHz, VL = 500 mVPP –76
f = 500 MHz, VL = 500 mVPP –59
f = 1 GHz, VL = 500 mVPP –53
IMD2 Second-order intermodulation distortion f = 500 MHz, VL = 0.25 VPP per tone –94 dBc
f = 1 GHz, VL = 0.25 VPP per tone –83
f = 2 GHz, VL = 0.25 VPP per tone –68
OIP2 Second-order output intercept point f = 500 MHz, VL = 1 VPP, matched load 70 dBm
f = 1000 MHz, VL = 1 VPP, matched load 54
IMD3 Third-order intermodulation distortion f = 500 MHz, VL = 0.25 VPP per tone –74 dBc
f = 1 GHz, VL = 0.25 VPP per tone –63
f = 2 GHz, VL = 0.25 VPP per tone –49
OIP3 Third-order output intercept point f = 500 MHz, VL = 1 VPP, unmatched load 33 dBm
f = 1000 MHz, VL = 1 VPP, unmatched load 26.5
NOISE PERFORMANCE
en Input voltage noise density 1.25 nV/√Hz
in Input noise current 3.5 pA/√Hz
NF Noise figure RS = 50 Ω, SE-DE, G = 12 dB,
200 MHz		 11.9 dB
INPUT
VIO Input offset voltage ±0.5 ±5 mV
IIB Input bias current 70 150 µA
IIO Input offset current ±1 ±20 µA
Zid Differential impedance 4600 Ω
VICL Input common-mode
low voltage		 [1, 2, 3] (VS–) (VS–) + 0.41 V
VICH Input common-mode
high voltage 		[1, 2, 3] (VS+) – 1.41 (VS+) – 1.2 V
CMRR Common-mode rejection ratio Differential, 1-VPP input shift, dc –72 dBc
OUTPUT
VOCRH Output voltage range, high Measured single-ended [1, 2, 3] (VS+) – 1.3 (VS+) – 1.1 V
VOCRL Output voltage range, low Measured single-ended [1, 2, 3] (VS–) + 1.3 (VS–) + 1.1 V
VOD Differential output voltage swing Differential 2.8 VPP
IOD Differential output current VO = 0 V(2) [1, 2, 3] 30 40 mA
POWER SUPPLY
VS Supply voltage [1, 2, 3] 3.15 5.25 V
PSRR Power-supply rejection ratio VS– [1, 2, 3] –80 –44 dB
VS+ [1, 2, 3] –84 –48
IQ Quiescent current PD = 0 [1, 2, 3] 44 54 63 mA
PD = 1 [1, 2, 3] 1 1.6 5
OUTPUT COMMON-MODE CONTROL PIN (VCM)
SSBW Small-signal bandwidth VOCM = 200 mVPP 3 GHz
VCM voltage range low Differential gain shift < 1 dB [1, 2, 3] (VS–) + 1.35 (VS–) + 1.55 V
VCM voltage range high Differential gain shift < 1 dB [1, 2, 3] (VS+) – 1.55 (VS+) – 1.35 V
VCM gain VCM = 0 V [1, 2, 3] 0.98 1 1.01 V/V
VOCM output common-mode offset from VCM input voltage VCM = 0 V –27 mV
VOCM Common-mode offset voltage Output-referred 0.4 mV
POWER DOWN (PD PIN)
VT Enable or disable voltage threshold Device powers on below 0.8 V,
device powers down above 1.2 V		 [1, 2, 3] 0.9 1.1 1.2 V
Power-down quiescent current [1, 2, 3] 1 1.6 6 mA
PD bias current PD = 2.5 V [1, 2, 3] 10 ±100 µA
Turn-on time delay Time to VO = 90% of final value 10 ns
Turn-off time delay Time to VO = 10% of original value 10 ns
(1) For subgroup definitions, please see Table 1.

Table 1. Quality Conformance Inspection(1)

SUBGROUP DESCRIPTION TEMPERATURE (°C)
1 Static tests at 25
2 Static tests at 125
3 Static tests at –55
4 Dynamic tests at 25
5 Dynamic tests at 125
6 Dynamic tests at –55
7 Functional tests at 25
8A Functional tests at 125
8B Functional tests at –55
9 Switching tests at 25
10 Switching tests at 125
11 Switching tests at –55
(1) MIL-STD-883, Method 5005 - Group A