SBOS849B December   2017  – February 2019 LMH5401-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      LMH5401-SP Small Signal Frequency Response
      2.      LMH5401-SP Driving an ADC12D1620QML
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3.3 V
    7. 7.7 Typical Characteristics: 5 V
    8. 7.8 Typical Characteristics: 3.3 V
  8. 8 Parameter Measurement Information
    1. 8.1  Output Reference Nodes and Gain Nomenclature
    2. 8.2  ATE Testing and DC Measurements
    3. 8.3  Frequency Response
    4. 8.4  S-Parameters
    5. 8.5  Frequency Response with Capacitive Load
    6. 8.6  Distortion
    7. 8.7  Noise Figure
    8. 8.8  Pulse Response, Slew Rate, and Overdrive Recovery
    9. 8.9  Power Down
    10. 8.10 VCM Frequency Response
    11. 8.11 Test Schematics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully-Differential Amplifier
      2. 9.3.2 Operations for Single-Ended to Differential Signals
        1. 9.3.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.3.2.2 DC-Coupled Input Signal Path Considerations for SE-DE Conversions
        3. 9.3.2.3 Resistor Design Equations for Single-to-Differential Applications
        4. 9.3.2.4 Input Impedance Calculations
      3. 9.3.3 Differential-to-Differential Signals
        1. 9.3.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.3.3.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      4. 9.3.4 Output Common-Mode Voltage
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation With a Split Supply
      2. 9.4.2 Operation With a Single Supply
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Stability, Noise Gain, and Signal Gain
      2. 10.1.2 Input and Output Headroom Considerations
      3. 10.1.3 Noise Analysis
      4. 10.1.4 Noise Figure
      5. 10.1.5 Thermal Considerations
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Driving Matched Loads
        2. 10.2.2.2 Driving Unmatched Loads For Lower Loss
        3. 10.2.2.3 Driving Capacitive Loads
        4. 10.2.2.4 Driving ADCs
          1. 10.2.2.4.1 SNR Considerations
          2. 10.2.2.4.2 SFDR Considerations
          3. 10.2.2.4.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
          4. 10.2.2.4.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
        5. 10.2.2.5 GSPS ADC Driver
        6. 10.2.2.6 Common-Mode Voltage Correction
        7. 10.2.2.7 Active Balun
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Do:
      2. 10.3.2 Don't:
  11. 11Power Supply Recommendations
    1. 11.1 Supply Voltage
    2. 11.2 Single Supply
    3. 11.3 Split Supply
    4. 11.4 Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Output Reference Nodes and Gain Nomenclature

The LMH5401-SP is a decompensated, fully-differential amplifier (FDA) configurable with external resistors for noise gain greater than 4 V/V or 12 dB (GBP = 6.5 GHz). For most of this document, data are collected for Gv = 17 dB for both single-ended-to-differential (SE-DE) and differential-to-differential (DE-DE) conversions in the diagrams illustrated in the Test Schematics section. When matching the output to a 100-Ω load, the evaluation module (EVM) uses external 40-Ω resistors to complete the output matching, as the device has an internal series 10 Ω on each output. Having on-chip output resistors creates two potential reference points for measuring the output voltage. The amplifier output pins create one output reference point (OUT_AMP). The other output reference point is OUT_LOAD at the 100-Ω load impedance, RL. These points are illustrated in Figure 53; see also the Test Schematics section.

LMH5401-SP 001_SBOS849_REF_NOMENCLATURE.gifFigure 53. Output Reference Nodes

Most measurements in the Electrical Characteristics tables and in the Typical Characteristics sections are measured with reference to the OUT_AMP reference point. Equation 1 shows that the conversion between reference points is a straightforward reduction of 3 dB for power and 6 dB for voltage in a matched condition when Ro is set such that 20 Ω + 2 × Ro = RL. With Ro set to 40 Ω and RL set to 100 Ω-differential, the total load impedance seen by the amplifier, RLtotal, is 200 Ω. This is considered a matched load condition as 100-Ω is driving RL of 100 Ω. The device is also capable of driving lower impedances. By setting Ro to 0 Ω, RLtotal becomes 120 Ω. This is considered an unmatched condition since 20 Ω is driving RL of 100 Ω. As explained in the Application Curves section, efficiency is improved (losses reduced) in a mismatched condition which is acceptable if transmission line reflections are avoided and proper termination practices are employed. As stated previously, most measurements in this document are referenced to OUT_AMP node. However, there are some typical characteristic plots that are measured with a fixed signal swing with respect to the OUT_LOAD reference point; specifically, IMD3 Figure 25 and Figure 27 are referenced to the voltage swing at node OUT_LOAD.

Equation 1. VOUT_LOAD = (VOUT_AMP – 6 dB) and POUT_LOAD = (POUT_AMP – 6 dB)

This document makes references to both voltage gain, Gv, and power gain, Gp. Voltage gain is defined as the ratio of the differential output voltage at node OUT_AMP to the differential, or single-ended, input voltage at the node before Rg. Power gain, for the purposes of this document, is defined as the ratio of the power dissipated on RL (100 Ω-differential) to the power transferred from a source to the input impedance of the amplifier. Whereas voltage gain contains no input and load impedances in its calculation, power gain does depend on termination impedances.