SBOSA87A December   2021  – November 2022 LMH5485-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Vs+ – Vs- = 5 V
    6. 7.6 Electrical Characteristics: Vs+ – Vs- = 3 V
    7. 7.7 Typical Characteristics: 5 V Single Supply
    8. 7.8 Typical Characteristics: 3 V Single Supply
    9. 7.9 Typical Characteristics: 3 V to 5 V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics: Vs+ – Vs- = 5 V

at TA = -55℃ to 125℃, VOCM = open (defaults midsupply), Vout = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = Vs+, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a 2-V/V test circuit, and Figure 8-2 for a DC-coupled gain of a 2-V/V test circuit.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth Vout = 100 mVPP, G = 1 590 MHz
Vout = 100 mVPP, G = 2 495
Vout = 100 mVPP, G = 5 185
Vout = 100 mVPP, G = 10 110
GBWP Gain-bandwidth product Vout = 100 mVPP, G = 20 850
LSBW Large-signal bandwidth Vout = 2 VPP 295
Bandwidth for 0.1-dB flatness Vout = 2 VPP 125
Slew rate(1) Vout = 2-VPP, FPBW 1300 V/µs
Rise/fall time Vout = 2-V step, input ≤ 0.5 ns tr 1.3 ns
Settling time Vout = 2-V step,
tr = 2 ns		 To 1% 4
To 0.1% 8
Overshoot and undershoot Vout = 2-V step, input ≤ 0.3 ns tr 10%
HD 100-kHz harmonic distortion Vout = 2 VPP HD2 –118 dBc
HD3 –147
10-MHz harmonic distortion Vout = 2 VPP HD2 –90
HD3 –102
2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) –90
3rd-order intermodulation distortion –85
en Input voltage noise f > 100 kHz 2.4 nV/√Hz
in Input current noise f > 1 MHz 1.9 pA/√Hz
Overdrive recovery time 2x output overdrive, either polarity 20 ns
ZOUT Closed-loop output impedance f = 10 MHz (differential) 0.1 Ω
DC PERFORMANCE
AOL Open-loop voltage gain 97 119 dB
VOS Input-referred offset voltage –900 ±100 900 µV
Input offset voltage drift(2) –2.5 ±0.5 2.5 µV/°C
IB+, IB– Input bias current Positive out of node 1.7 10 15 µA
Input bias current drift(2) 6 15 nA/°C
IOS Input offset current –650 ±150 650 nA
Input offset current drift(2) –1.5 ±0.3 1.5 nA/°C
INPUT
VICML Common-mode input low < 3-dB degradation in CMRR from midsupply (Vs–) – 0.2 Vs– V
VICMH Common-mode input high (Vs+) – 1.3 (Vs+) –1.2
CMRR Common-mode rejection ratio Input pins at midsupply 82 100 dB
Input impedance differential mode Input pins at midsupply 110 || 0.9 kΩ || pF
OUTPUT
Output voltage low (Vs–) + 0.2 (Vs–) + 0.25 V
Output voltage high (Vs+) – 0.25 (Vs+) – 0.2
Output current drive ±75 ±100 mA
POWER SUPPLY
IQ Quiescent operating current 9.2 10.1 11 mA
PSRR Power-supply rejection ratio Either supply pin to differential Vout 82 100 dB
POWER DOWN
VEN Enable voltage threshold (Vs–) + 1.7 V
VDIS Disable voltage threshold (Vs–) + 0.7
Disable pin bias current PD = Vs– → Vs+ 20 50 nA
Power-down quiescent current PD = (Vs–) + 0.7 V 6 30 µA
PD = Vs– 2 8
Turnon-time delay Time from PD = low to
Vout = 90% of final value		 100 ns
Turnoff time delay Time from PD = low to
Vout = 10% of final value		 60
OUTPUT COMMON-MODE VOLTAGE CONTROL(3)
Small-signal bandwidth VOCM = 100 mVPP 150 MHz
Slew rate(1) VOCM = 2-V step 400 V/µs
Gain 0.975 0.982 0.995 V/V
Input bias current Considered positive out of node –0.8 0.1 0.8 µA
Input impedance VOCM input driven to midsupply 47 || 1.2 kΩ || pF
Default voltage offset from midsupply VOCM pin open –45 ±8 45 mV
Common-mode offset voltage VOCM input driven to midsupply –8 ±2 8
CM VOS drift(2) VOCM input driven to midsupply –20 ±4 +20 µV/°C
Common-mode loop supply headroom to negative supply < ±15-mV shift from midsupply CM VOS 0.94 V
Common-mode loop supply headroom to positive supply < ±15-mV shift from midsupply CM VOS 1.2
(1) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) × 2π × f–3dB.
(2) Input offset voltage drift, input bias current drift, input offset current drift, and VOCM drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.
(3) Specifications are from the input VOCM pin to the differential output average voltage.