Refer to the PDF data sheet for device specific package drawings
The LMH6518 is a digitally controlled variable gain amplifier with a total gain that varies from –1.16dB to 38.8dB for a 40dB range in 2dB steps. The −3dB bandwidth is 900MHz at all gains. Gain accuracy at each setting is typically 0.1dB. When used in conjunction with TI's gigasamples per second (GSPS) ADC with adjustable full-scale range, the LMH6518 gain adjustment accommodates full scale input signals from 6.8mVPP to 920mVPP to get 700mVPP nominal at the ADC input. The auxiliary output (+OUT AUX and −OUT AUX) follows the main output and is intended for use in oscilloscope trigger function circuitry, but can have other uses in other applications.
The LMH6518 gain is programmed through a SPI-compatible serial bus. A signal path combined gain resolution of 8.5mdB is achieved when the device gain and the GSPS ADC FS input are both manipulated. Inputs and outputs are dc-coupled. The outputs are differential with individual common-mode voltage control (for main and auxiliary outputs), and have selectable bandwidth limiting circuitry (common to both main and auxiliary) of 20MHz, 100MHz, 200MHz, 350MHz, 650MHz, 750MHz, or full BW.
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | +OUT AUX | O | Auxiliary positive output |
2 | −OUT AUX | O | Auxiliary negative output |
3 | VCC | P | Analog power supply |
4 | VCC | P | Analog power supply |
5 | GND | G | Ground, electrically connected to the WQFN heat sink |
6 | +IN | I | Positive input |
7 | –IN | I | Negative input |
8 | GND | G | Ground, electrically connected to the WQFN heat sink |
9 | CS | I | Serial chip select (SPI, active low): While this signal is asserted, SCLK is used to accept serial data present on SDIO and to source serial data on SDIO. When this signal is deasserted, SDIO is ignored and SDIO is in a high-impedance state. |
10 | SDIO | I/O | Serial data-in or data-out (SPI). During a write operation, serial data are shifted into the device (8-bit command and 16-bit data) on this pin while CS signal is asserted. During a read operation, serial data are shifted out of the device on this pin while CS signal is asserted. At other times, and after one complete access cycle (24 bits; see Figure 6-1 and Figure 6-2), this input is ignored. This output is in a high-impedance state when CS is deasserted. This pin is bidirectional. |
11 | SCLK | I | Serial clock (SPI): Serial data are shifted into and out of the device synchronous with this clock signal. SCLK transitions with CS deasserted are ignored. To minimize digital crosstalk, stop SCLK when not used. |
12 | VDD | P | Digital power supply |
13 | VCM | I | Input from ADC to control main output common mode (CM) voltage |
14 | −OUT | O | Main negative output |
15 | +OUT | O | Main positive output |
16 | VCM_AUX | I | Input to control auxiliary output CM voltage |
Pad | Thermal Pad | — | Thermal pad (WQFN heat sink), electrically connected to pins 5 and 8 (GND) |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Analog supply voltage (5 V nominal) | 5.5 | V | ||
VDD | Digital supply voltage (3.3 V nominal) | 3.6 | |||
Differential input signal voltage | ±1 | V | |||
Maximum dc output value(2) | 1700 | mVPP | |||
Input common mode voltage | 1 | 4 | V | ||
VCM and VCM_Aux | 2 | V | |||
SPI inputs | 3.6 | V | |||
Soldering temperature | Infrared or convention (20 s) | 235 | °C | ||
Wave (10 s) | 260 | ||||
TJ | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Machine model (MM) | ±200 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Analog supply voltage | 5 ±5% | V | ||
VDD | Digital supply voltage | 3.3 ±5% | V | ||
TA | Ambient temperature | –40 | 85 | °C |
THERMAL METRIC(1) | LMH6518 | UNIT | |
---|---|---|---|
RGH (WQFN) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 31.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 11.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 11.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(2) | TYP(3) | MAX(2) | UNIT | ||
---|---|---|---|---|---|---|---|
DYNAMIC PERFORMANCE | |||||||
LSBW | –3-dB bandwidth | All gains | 900 | MHz | |||
Peaking | All gains | 1 | dB | ||||
GF_0.1 dB | ±0.1-dB gain flatness | All gains | 150 | MHz | |||
GF_1 dB | ±1-dB gain flatness | All gains | 400 | MHz | |||
TRS | Rise time | 460 | ps | ||||
TRL | Fall time | 450 | |||||
OS | Overshoot | Main output | 9% | ||||
ts_1 | Settling time | Main output, ±0.5% | 10 | ns | |||
ts_2 | Settling time | Main output, ±0.05% | 14 | ||||
t_recover | Recovery time(4) | All gains | <5 | ns | |||
PD | Propagation delay | VOUT = 0.7 VPP, all gains | 1.2 | ns | |||
PD_VAR | Propagation delay variation | Gain varied | 100 | ps | |||
NOISE, DISTORTION, AND RF SPECIFICATIONS | |||||||
en_1 | Input noise spectral density | Max gain, 10 MHz | 0.98 | nV/√ Hz | |||
en_2 | Input noise spectral density | Preamp LG and 0-dB ladder, 10 MHz |
4.1 | nV/√ Hz | |||
eno_1 | RMS output noise | Max gain, 100 Hz to 400 MHz | 1.7 | mV | |||
eno_2 | RMS output noise | Preamp LG, 0-dB ladder, 100 Hz to 400 MHz |
940 | µV | |||
NF_1 | Noise figure | Max gain, RS = 50 Ω each input, 10 MHz |
3.8 | dB | |||
NF_2 | Noise figure | Preamp LG, 0-dB ladder, RS = 50 Ω each input, 10 MHz |
13.5 | dB | |||
HD2_1 | 2nd harmonic distortion(5) | Main output, 100 MHz, all gains | –50 | dBc | |||
HD3_1 | 3rd harmonic distortion(5) | Main output, 100 MHz, all gains | –53 | dBc | |||
HD2_2 | 2nd harmonic distortion(5) | Auxiliary output, 100 MHz, all gains | –48 | dBc | |||
HD3_2 | 3rd harmonic distortion(5) | Auxiliary output, 100 MHz, all gains | –50 | dBc | |||
HD2_3 | 2nd harmonic distortion(5) | Main output, 250 MHz, all gains | –44 | dBc | |||
HD3_3 | 3rd harmonic distortion(5) | Main output, 250 MHz, all gains | –50 | dBc | |||
HD2/HD3_4 | 2nd and 3rd harmonic distortion(5) | Auxiliary output, 250 MHz, all gains | –42 | dBc | |||
IMD3 | Intermodulation distortion(5) | f = 250 MHz, main output | –65 | dBc | |||
OIP3_1 | Intermodulation intercept(5) | Main output, 250 MHz | 26 | dBm | |||
P_1dB_main | –1-dB compression | Main output, 250 MHz, 0-dB ladder | 1.8 | VPP | |||
Main output, 250 MHz, 20-dB ladder | 1 | ||||||
P_1dB_aux | –1-dB compression | Auxiliary output, 250 MHz, 0-dB ladder |
1.65 | VPP | |||
Auxiliary output, 250 MHz, 20-dB ladder |
1 | ||||||
GAIN PARAMETERS | |||||||
AV_DIFF_MAX | Maximum gain | 38.1 | 38.8 | 39.5 | dB | ||
AV_DIFF_MIN | Minimum gain | –1.91 | –1.16 | –0.4 | dB | ||
Gain_Step | Gain step size | All gains including preamp step | 1.8 | 2 | 2.2 | dB | |
Gain step
size with ADC (see Section 7) |
ADC FS adjusted | 8.5 | mdB | ||||
Gain_Range | Gain range | 39 | 40 | 41 | dB | ||
TC_AV_DIFF | Gain temp coefficient(6) | All gains | –0.8 | mdB/°C | |||
Gain_ACC | Absolute gain accuracy | Compared to theoretical from max gain in 2-dB steps |
0.75 | 0.75 | dB | ||
MATCHING | |||||||
Gain_match | Gain
matching, main and auxiliary |
All gains | ±0.1 | ±0.2 | dB | ||
BW_match | –3-dB
bandwidth matching, main and auxiliary |
All gains | 5% | ||||
RT_match | Rise time
matching, main and auxiliary |
All gains | 5% | ||||
PD_match | Propagation
delay matching, main and auxiliary |
All gains | 100 | ps | |||
ANALOG I/O | |||||||
CMRR_1 | CM rejection ratio (see Table 8-1) | Preamp HG, 0-dB ladder, 1.9 V < CMVR < 3.1 V |
45 | 86 | dB | ||
CMRR_2 | CM rejection ratio (see Table 8-1) | Preamp LG, 0-dB ladder, 1.9 V < CMVR < 3.1 V |
40 | 55 | dB | ||
CMVR_1 | Input common-mode voltage | Preamp HG, all ladder steps, CMRR ≥ 45 dB |
1.9 | 3.1 | V | ||
CMVR_2 | Input common-mode voltage | Preamp LG, all ladder steps, CMRR ≥ 40 dB |
1.9 | 3.1 | V | ||
|ΔVO_CM|ΔI_CM| | All gains, 2 V < CMVR < 3 V | –60 | –100 | dB | |||
CMRR_CM | CM rejection ratio relative to VCM (see Table 8-1) | Preamp LG, 0 dB | 101 | dB | |||
Zin_diff | Differential input impedance | All gains | 150 || 1.5 | kΩ || pF | |||
Zin_CM | CM input impedance | Preamp HG | 420 || 1.7 | kΩ || pF | |||
Preamp LG | 900 || 1.7 | ||||||
FSOUT1 | Full scale voltage swing | Main output, all gains, THD at 100 MHz ≤ –40 dBc |
770(7) | 800 | mVPP | ||
FSOUT2 | Full scale voltage swing | Main output, clamped, 0‑dB ladder | 1800 | 1960 | mVPP | ||
FSOUT3 | Full scale voltage swing | Auxiliary output, all gains THD at 100 MHz ≤ –40 dBc |
770(7) | 800 | mVPP | ||
FSOUT4 | Full scale voltage swing | Auxiliary output, clamped, 0-dB ladder | 1600 | 1760 | mVPP | ||
VOUT_MAX1 | Voltage at
each output pin (clamped) |
Main output, all gains, VCM = 1.2 V | 0.5 | 1.8 | V | ||
VOUT_MAX2 | Voltage at
each output pin (clamped) |
Auxiliary output, all gains, VCM = 1.2 V |
0.8 | 2.2 | V | ||
VOUT_MAX3 | Voltage at
each output pin (clamped) |
Main output, all gains, VCM = 1.45 V | 2.05 | V | |||
VOUT_MAX4 | Voltage at
each output pin (clamped) |
Auxiliary output, all gains, VCM = 1.45 V |
2.45 | V | |||
ZOUT_DIFF | Differential output impedance | All gains | 92 | 100 | 108 | Ω | |
VOOS | Output offset voltage | All gains | ±15 | ±40 | mV | ||
VOOS_shift1 | Output offset voltage shift | Preamp LG to preamp HG | 13.7 | mV | |||
VOOS_shift2 | Output offset voltage shift | All gains, excluding preamp step | 12.7 | mV | |||
TCVOOS | Output offset voltage drift(6) | Preamp HG, 0-dB ladder | –24 | µV/°C | |||
Preamp LG, 0-dB ladder | –7 | ||||||
IB | Input bias current(8) | TA = –40°C to +85°C | 40 | 100 | µA | ||
TA = –65°C to +150°C | 140 | ||||||
VOCM | Output CM voltage | All gains | TA = –40°C to +85°C | 1.2 | V | ||
TA = –65°C to +150°C | 0.95 | 1.45 | |||||
VOS_CM | Output CM offset | All gains | ±15 | ±30 | mV | ||
TC_VOS_CM | CM offset
voltage temperature coefficient |
All gains | +55 | µV/°C | |||
BAL_Error_DC | Output gain balance error |
![]() |
–78 | dB | |||
BAL_Error_AC | Output gain balance error |
![]() |
–45 | dB | |||
PB | Phase balance error (see Table 8-1) | 250 MHz | ±0.8 | deg | |||
PSRR | Differential power-supply rejection (see Table 8-1) | Preamp HG, 0-dB ladder | –60 | –87 | dB | ||
Preamp LG, 0-dB ladder | –50 | –70 | |||||
PSRR_CM | CM power-supply rejection (see Table 8-1) | Preamp LG, 0-dB ladder | –55 | –71 | dB | ||
VCM_I | VCM input bias current(8) | All gains | TA = –40°C to +85°C | ±1 | ±10 | nA | |
TA = –65°C to +150°C | ±20 | ||||||
VCM_AUX_I | VCM_AUX input bias current(8) | All gains | TA = –40°C to +85°C | ±1 | ±10 | nA | |
TA = –65°C to +150°C | ±20 | ||||||
DIGITAL I/O | |||||||
VIH | Input logic high | TA = –65°C to +150°C | VDD – 0.6 | V | |||
VIL | Input logic low | TA = –65°C to +150°C | 0.5 | V | |||
VOH | Output logic high | VDD | V | ||||
VOL | Output logic low | 0 | V | ||||
RHi_Z | Output resistance | High-impedance mode | 5 | MΩ | |||
I_in | Input bias current | <1 | µA | ||||
FSCLK | SCLK rate | 10 | MHz | ||||
FSCLK_DT | SCLK duty cycle | 45% | 50% | 55% | |||
POWER REQUIREMENTS | |||||||
IS1 | Supply current, VCC | TA = –40°C to +85°C | 195 | 210 | 225 | mA | |
TA = –65°C to +150°C | 230 | ||||||
IS1_off | Supply current, VCC aux off | TA = –40°C to +85°C | 150 | 165 | mA | ||
TA = –65°C to +150°C | 170 | ||||||
IDD | Supply current, VDD | TA = –40°C to +85°C | 180 | 350 | µA | ||
TA = –65°C to 150°C | 400 | ||||||
BANDWIDTH LIMITING FILTER SPECIFICATIONS | |||||||
Pass band tolerance, –3 dB bandwidth |
All gains | 20 MHz | 0% | 20% | |||
100 MHz | 0% | 20% | |||||
200 MHz | 0% | 20% | |||||
350 MHz | ±25% | ||||||
650 MHz | ±25% | ||||||
750 MHz | ±25% | ||||||
Preamp LG, 0-dB ladder |
350 MHz | ±10% | |||||
650 MHz | ±10% | ||||||
750 MHz | ±10% |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tS | SDIO setup time | 25 | ns | ||
tH | SDIO hold time | 25 | ns | ||
tCES | CS enable setup time (from CS asserted to rising edge of SCLK) | 25 | ns | ||
tCDS | CS disable setup time (from CS deasserted to rising edge of SCLK) | 25 | ns | ||
tIAG | Inter-access gap | 3 | SCLK cycles |
at input CM = 2.5-V, VCM =
1.2-V, VCM AUX = 1.2-V, single-ended input drive, VCC = 5-V,
VDD = 3.3-V,
RL = 100 Ω
differential (both main and auxiliary outputs), VOUT = 0.7 VPP
differential (both main and auxiliary outputs), main output specification (auxiliary
is labeled), full bandwidth setting, gain = 18.8-dB (preamp LG, 0-dB ladder
attenuation), and full power setting (with auxiliary output turned on) (unless
otherwise noted)
The LMH6518 is a digitally-controlled variable gain amplifier (DVGA) that is designed specifically as an oscilloscope analog front end (AFE). This device samples an analog voltage and conditions the voltage for the analog to digital converter (ADC) input. This device is specifically designed to drive TI's giga sample ADCs that have a 100-Ω input impedance and 800 mVPP full-scale input voltage.
The LMH6518 offers several unique features in addition to being a general purpose digital variable gain amplifier (DVGA).
The LMH6518 has a fully differential preamplifier which has a consistent 150-kΩ impedance across all gain settings. The LMH6518 is also driven with a single-ended signal source. The preamplifier has two gain settings. See Section 7.2.1.2.2 for details.
The LMH6518 has two nearly identical amplifiers. The output amplifier was designed as the primary output amplifier. The output amplifier features an internal 100-Ω termination that interfaces with 100-Ω input impedance ADCs. The output amplifier has a common-mode voltage control pin that sets the output common-mode voltage of the amplifier.