SNOSB21E May   2008  – July 2024 LMH6518

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Preamplifier
        1. 6.3.1.1 Primary Output Amplifier
        2. 6.3.1.2 Auxiliary Amplifier
      2. 6.3.2 Overvoltage Clamp
      3. 6.3.3 Attenuator
      4. 6.3.4 Digital Control Block
    4. 6.4 Device Functional Modes
      1. 6.4.1 Primary Amplifier
      2. 6.4.2 Auxiliary Output
    5. 6.5 Programming
      1. 6.5.1 Logic Functions
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Oscilloscope Front End
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Settings and ADC SPI Code (ECM)
          2. 7.2.1.2.2 Input and Output Considerations
            1. 7.2.1.2.2.1 Output Swing, Clamping, and Operation Beyond Full Scale
          3. 7.2.1.2.3 Oscilloscope Trigger Applications
        3. 7.2.1.3 Application Curves
      2. 7.2.2 JFET LNA Implementation
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Attenuator Design
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGH|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.1 Design Requirements

This circuit uses an N-Channel JFET (J10) in source-follower configuration to buffer the input signal with J8 acting as a constant current source. This buffer presents a fixed input impedance (1 MΩ || 10 pF) with a gain close to 1‑V/V.

The signal path is ac-coupled through C7 with dc (and low frequency) at LMH6518 +IN maintained through the action of U1. NPN transistor Q0 is an emitter follower which isolates the buffer from the load (LMH6518 input and board traces).

The undriven input of the LMH6518 (−IN) is biased to 2.5-V by R6, R9 voltage divider. The lower half of U1 inverts this voltage and the upper half of U1 compares this voltage to the combination of the driven output level at LMH6518 +IN and the scaled version of scope input at R14, R21 junction, and adjusts J10 Gate accordingly to set the LMH6518 +IN. This control loop has a frequency response that covers dc to a few Hz, limited by roll-off capacitor C3 and R15 combination (first order approximation). DC and low-frequency gain is given by Equation 18.

Equation 18. LMH6518

With the values in Figure 7-11 → R2 approximately 452 kΩ.

For a flat frequency response, the dc (low frequency) gain requires lowering to match the less-than-1 V/V ac (high frequency) path gain through the JFETs. This is done by increasing the value of R2.

Choose values of R15 and R11 so that the frequency response at J10 Gate (and consequently the output) remain flat when C7 starts to conduct as in Equation 19.

Equation 19. LMH6518

Offset correction is done by varying the voltage at R4, using a DAC or equivalent as shown, to shift the LMH6518 +IN voltage relative to −IN. The result is a circuit which shifts the ground referenced scope input to 2.5‑V (VCC / 2) CM with adjustable offset and without any JFET or BJT related offsets.

The front-end attenuator (not shown) lower leg resistance is increased for proper divider-ratio to account for the 1-MΩ shunt due to the series combination of R21 and R14. For example, a 10:1 front-end attenuator is formed by a series 900 kΩ and a shunt 111 kΩ for a scope BNC input impedance of 1 MΩ (= 900 K + (111 K || 1 M)).

Table 7-3 lists other possible JFET candidates that fall in the range of speed (ft) and low-noise requirement.

Table 7-3 Selected JFET Candidates Specifications
COMPANYPART NUMBERVP (V)Idss (mA)gm (mS)INPUT C
(pF)		NOISE(1)
(nV/RtHz)		BREAK
DOWN (V)		CALCULATED ft (MHz)
InterfetIF140–2.2105.52.34–20380
InterfetIF142–2.2105.52.34–25380
Interfet2N5397/8–2.513852.5–25254
Interfet2N5911/2–2.513852.5—254
InterfetJ308/9/10–2.321175.8—–25466
PhilipsBF513–315105——318
FairchildMMBF5486–414742.5–25278
Vishay SiliconixSST441–3.51363.54–35272
(1) Noise data at approximately Idss / 2.

The LNA noise can degrade the scope SNR if comparable to the input-referred noise of the LMH6518. LNA noise is influenced by the following operating conditions:

  1. JFET equivalent input noise
  2. BJT base current

Reducing either a or b above, or both, reduces noise. One way to reduce a is to increase R8 (currently set to 0 Ω). This reduces the noise impact of J8 but requires a JFET which has a higher Idss rating to maintain the operating current of J10, so that the J10 noise contribution is minimized. Reducing the BJT base current is accomplished with increasing R20 at the expenses of higher rise and fall times. A higher β also reduces the base current (keep in mind that β and ft at the operating collector current is what matters).

Figure 7-13 shows the impact of the JFET buffer noise on SNR, compared to SNR in Figure 7-3, assuming either 3‑nV/√Hz or 1.5-nV/√Hz buffer noise for comparison.