SNOSB47E May   2011  – August 2016 LMH6521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Characteristics
      2. 7.3.2 Output Characteristics
      3. 7.3.3 Output Connections
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Digital Control
      2. 7.5.2 Parallel Mode (MOD1 = 1, MOD0 = 1)
      3. 7.5.3 Serial Mode: SPI Compatible Interface (MOD1 = 1, MOD0 = 0)
      4. 7.5.4 Pulse Mode (MOD1 = 0, MOD0 = 1)
      5. 7.5.5 Interface to ADC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • OIP3 of 48.5 dBm at 200 MHz
  • Maximum Voltage Gain of 26 dB
  • Gain Range: 31.5 dB with 0.5-dB Step Size
  • Channel Gain Matching of ±0.04 dB
  • Noise Figure: 7.3 dB at Maximum Gain
  • –3-dB Bandwidth of 1200 MHz
  • Low Power Dissipation
  • Independent Channel Power Down
  • Three Gain Control Modes:
    • Parallel Interface
    • Serial Interface (SPI)
    • Pulse Mode Interface
  • Temperature Range: –40°C to +85°C
  • Thermally-Enhanced, 32-Pin WQFN Package

2 Applications

  • Cellular Base Stations
  • Wideband and Narrowband IF Sampling Receivers
  • Wideband Direct Conversion
  • Digital Pre-Distortion
  • ADC Drivers

3 Description

The LMH6521 contains two high performance, digitally controlled variable gain amplifiers (DVGA).

Both channels of the LMH6521 have an independent, digitally controlled attenuator followed by a high linearity, differential output amplifier. Each block has been optimized for low distortion and maximum system design flexibility. Each channel has a high speed power down mode.

The internal digitally controlled attenuator provides precise 0.5-dB gain steps over a 31.5-dB range. Serial and parallel programming options are provided. Serial mode programming uses the SPI interface. A pulse mode is also offered where simple up or down commands can change the gain one step at a time.

The output amplifier has a differential output allowing 10-VPPD signal swings on a single 5-V supply. The low impedance output provides maximum flexibility when driving filters or analog to digital converters.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMH6521 WQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

LMH6521 Block Diagram

LMH6521 30120102.gif

Channel Matching Error (Ch A – Ch B)

LMH6521 30120180.gif