SNOSB47E May   2011  – August 2016 LMH6521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Characteristics
      2. 7.3.2 Output Characteristics
      3. 7.3.3 Output Connections
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Digital Control
      2. 7.5.2 Parallel Mode (MOD1 = 1, MOD0 = 1)
      3. 7.5.3 Serial Mode: SPI Compatible Interface (MOD1 = 1, MOD0 = 0)
      4. 7.5.4 Pulse Mode (MOD1 = 0, MOD0 = 1)
      5. 7.5.5 Interface to ADC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RTV Package
32-Pin WQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 A3/SDI/DNA I A3: Attenuation bit three = 4-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
SDI: Serial data in. Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible. See Application Information for more details.
DNA: Down pulse pin. A logic 0 pulse decreases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 2 resets the gain to maximum gain.
2 A4/CLK/UPA I A4: Attenuation bit four = 8-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
CLK: Serial clock. Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible.
UPA: Up pulse pin. A logic 0 pulse increases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 1 resets the gain to maximum gain.
3 A5 I Attenuation bit five = 16-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect to DC ground. Pins unused in pulse mode, connect to DC ground.
4 MOD0 I Digital mode control pins. These pins float to the logic hi state if left unconnected. Pins unused in serial mode, connect to DC ground. See Application Information for mode settings.
5 MOD1 I Digital mode control pins. These pins float to the logic hi state if left unconnected. Pins unused in pulse mode, connect to DC ground. See Application Information for mode settings.
6 B5 I Attenuation bit five = 16-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect to DC ground. Pins unused in pulse mode, connect to DC ground.
7 B4/UPB I B4: Attenuation bit four = 8-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
UPB: Up pulse pin. A logic 0 pulse increases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 8 resets the gain to maximum gain. Pins unused in serial mode, connect to DC ground.
8 B3/DNB I B3: Attenuation bit three = 4-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
DNB: Down pulse pin. A logic 0 pulse decreases gain one step. Digital inputs pulse mode
(MOD1 = 0, MOD0 = 1).
Pulsing this pin together with pin 7 resets the gain to maximum gain. Pins unused in serial mode, connect to DC ground.
9 B2/S1B I B2: Attenuation bit two = 2-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
S1B: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB. Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
Pins unused in serial mode, connect to DC ground.
10 B1/S0B I B1: Attenuation bit one = 1-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
S0B: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB. Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
Pins unused in serial mode, connect to DC ground.
11 INB+ I Amplifier noninverting input. Internally biased to mid supply. Input voltage must not exceed V+ or go below GND by more than 0.5 V.
12 INB– I Amplifier inverting input. Internally biased to mid supply. Input voltage must not exceed V+ or go below GND by more than 0.5 V.
13 GND P Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
14 +5V P Power supply pins. Valid power supply range is 4.75 V to 5.25 V.
15 GND P Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
16 B0 I Attenuation bit zero = 0.5-dB step. Gain steps down from maximum gain (000000 = Maximum Gain). Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect to DC ground. Pins unused in pulse mode, connect to DC ground.
17 OUTB+ O Amplifier noninverting output. Externally biased to 0 V.
18 OUTB– O Amplifier inverting output. Externally biased to 0 V.
19 ENB I Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
20 LATB I Latch pins. Logic zero = active, logic 1 = latched. Gain does not change once latch is high. Connect to ground if the latch function is not desired. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect to DC ground.
21 LATA I Latch pins. Logic zero = active, logic 1 = latched. Gain does not change once latch is high. Connect to ground if the latch function is not desired. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect to DC ground.
22 ENA I Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
23 OUTA– O Amplifier inverting output. Externally biased to 0 V.
24 OUTA+ O Amplifier noninverting output. Externally biased to 0 V.
25 A0 I Attenuation bit zero = 0.5-dB step. Gain steps down from maximum gain (000000 = Maximum Gain). Digital inputs parallel mode (MOD1 = 1, MOD0 = 1). Pins unused in serial mode, connect to DC ground. Pins unused in pulse mode, connect to DC ground.
26 GND P Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
27 +5V P Power supply pins. Valid power supply range is 4.75 V to 5.25 V.
28 GND P Ground pin. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
29 INA– I Amplifier inverting input. Internally biased to mid supply. Input voltage must not exceed V+ or go below GND by more than 0.5 V.
30 INA+ I Amplifier noninverting input. Internally biased to mid supply. Input voltage must not exceed V+ or go below GND by more than 0.5 V.
31 A1/SDO/S0A I A1: Attenuation bit one = 1-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
SDO: Serial data out. Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible.
S0A: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB. Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
32 A2/CS/S1A I A2: Attenuation bit two = 2-dB step. Digital inputs parallel mode (MOD1 = 1, MOD0 = 1).
CS: Serial chip select (active low). Digital inputs serial mode (MOD1 = 1, MOD0 = 0) SPI compatible.
S1A: Step size zero and step size 1. (0,0) = 0.5 dB; (0, 1)= 1 dB; (1,0) = 2 dB, and (1, 1)= 6 dB. Digital inputs pulse mode (MOD1 = 0, MOD0 = 1).
GND GND P Ground plane. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins.
(1) I = Input, O = Output, P = Power