SNOSB47E May   2011  – August 2016 LMH6521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Characteristics
      2. 7.3.2 Output Characteristics
      3. 7.3.3 Output Connections
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Digital Control
      2. 7.5.2 Parallel Mode (MOD1 = 1, MOD0 = 1)
      3. 7.5.3 Serial Mode: SPI Compatible Interface (MOD1 = 1, MOD0 = 0)
      4. 7.5.4 Pulse Mode (MOD1 = 0, MOD0 = 1)
      5. 7.5.5 Interface to ADC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Positive supply voltage (pin 14 and 27) –0.6 5.5 V
Differential voltage between any two grounds < 200 mV
Analog input voltage –0.6 V+ V
Digital input voltage –0.6 5.5 V
Soldering temperature, infrared or convection (30 s) 260 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1)(2) ±2000 V
Charged-device model (CDM)(3) ±750
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human-body model, applicable std. MIL-STD-883, Method 3015.7. Field-induced Charge-device model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Machine model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC).
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (pin 14 and 27) 4.75 5.25 V
Differential voltage between any two grounds <10 mV
Analog input voltage, AC coupled 0 V+ V
TA Ambient temperature(2) –40 85 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

THERMAL METRIC(1) LMH6521 UNIT
RTV (WQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 45 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23.7 °C/W
RθJB Junction-to-board thermal resistance 9.1 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 9.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

The following specifications apply for single supply with V+ = 5 V, differential VOUT = 4 VPP, RL= 200 Ω, TA = 25°C,
fin = 200 MHz, and maximum gain (0 attenuation)(1)
PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT
DYNAMIC PERFORMANCE
SSBW 3-dB small signal bandwidth 1200 MHz
Output noise voltage Amplifier output with RSOURCE = 200 Ω 33 nV/√Hz
Noise figure Source = 200 Ω 7.3 dB
OIP3 Output 3rd-order intercept point f = 100 MHz, PO= 4 dBm per tone 56 dBm
f = 200 MHz, PO= 4 dBm per tone 48.5
f = 250 MHz, PO= 4 dBm per tone 46.5
OIP2 Output 2nd-order intercept point f = 100 MHz, PO= 4 dBm per tone 92 dBm
f = 200 MHz, PO= 4 dBm per tone 80
f = 250 MHz, PO= 4 dBm per tone 73
HD2 2nd harmonic distortion f = 200 MHz, PO= 6 dBm –84 dBc
HD3 3rd harmonic distortion f = 200 MHz, PO= 6 dBm –83 dBc
P1dB 1-dB compression point 17 dBm
ANALOG I/O
Input resistance Differential 200 Ω
Input common mode voltage Self biased (AC coupled) 2.5 V
Input common mode voltage range Externally driven (DC coupled) 2 to 3 V
Maximum input voltage swing Differential 11 VPPD
Output resistance Differential 20 Ω
Maximum differential output voltage swing Differential 10 VPPD
CMRR Common mode rejection ratio DC, VID = 0 V, VCM = 2.5 V ±0.5 V 80 dB
PSRR Power supply rejection ratio DC, V+ = 5 V ±0.5 V, VIN = 2.5 V 77 dB
Channel to channel isolation f = 200 MHz, minimum attenuation setting 73 dB
GAIN PARAMETERS
Maximum voltage gain Gain Code 000000 (min. attenuation),
Av = VO / VIN		 26 dB
Minimum voltage gain Gain Code 111111 (max. attenuation),
Av = VO / VIN		 –5.5 dB
Gain accuracy 1%
Gain step size 0.5 dB
Channel gain matching ChA – ChB, any gain setting ±0.04 dB
Channel phase matching ChA – ChB, any gain setting ±0.45 °
Cumulative gain error 0 to 12 dB attenuation setting ±0.1 dB
0 to 24 dB attenuation setting ±0.3
0 to 31 dB attenuation setting ±0.5
Cumulative phase shift 0 to 12 dB attenuation setting ±0.6 °
0 to 24 dB attenuation setting ±5.3
0 to 31 dB attenuation setting ±16.5
Gain step switching time 15 ns
Gain temperature sensitivity 0 attenuation setting 2.7 mdB/°C
POWER REQUIREMENTS
VCC Supply voltage 4.75 5 5.25 V
ICC Supply current Both channels enabled TA = –40°C to 85°C 225 mA
TA = –65°C to 150°C 245
ICC Disabled supply current Both channels 35 mA
ALL DIGITAL INPUTS(4)
VIL Logic input low voltage 0.5 V
VIH Logic input high voltage 1.8 V
IIH Logic input high input current Digital input voltage = 5 V 200 µA
IIL Logic input low input current Digital input voltage = 0 V –60 µA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. No ensurance of parametric performance is indicated in the electrical tables under conditions different than those tested
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) Logic compatibility is TTL, 2.5-V CMOS, and 3.3-V CMOS.

6.6 Timing Requirements

MIN NOM MAX UNIT
PARALLEL AND PULSE MODE TIMING
tGS Setup time 3 ns
tGH Hold time 3 ns
tLP Latch low pulse width 7 ns
tPG Pulse gap between pulses 20 ns
tPW Minimum pulse width (pulse mode) 15 ns
tRW Reset width 10 ns
SERIAL MODE TIMING AND AC CHARACTERISTICS (SPI COMPATIBLE)
fSCLK Max serial clock frequency 50 MHz
tPH SCLK high state duty cycle 50% SCLK
tPL SCLK low state duty cycle 50% SCLK
tSU Serial data in setup time 2 ns
tH Serial data in hold time 2 ns
tOZD Serial data out TRI-STATE-to-driven time (referenced to negative edge of SCLK) 10 ns
tOD Serial data out output delay time (referenced to negative edge of SCLK) 10 ns
tCSS Serial chip select setup time (referenced to positive edge of SCLK) 5 ns

6.7 Typical Characteristics

V+ = 5 V, Differential VOUT = 4 VPP, RL = 200 Ω, TA = 25°C, fin = 200 MHz, and Maximum Gain (0 Attenuation)
LMH6521 30120174.gif Figure 1. Frequency Response 2-dB Gain Steps
LMH6521 30120179.gif Figure 3. OIP3 vs Frequency
LMH6521 30120177.gif Figure 5. OIP3 vs Pout
LMH6521 30120190.gif Figure 7. Third Order Harmonic Distortion
vs Frequency
LMH6521 30120195.gif Figure 9. Third Order Harmonic Distortion
vs Attenuation
LMH6521 30120193.gif Figure 11. Second Order Harmonic Distortion
at 100 MHz
LMH6521 30120191.gif Figure 13. Second Order Harmonic Distortion
at 200 MHz
LMH6521 30120173.gif Figure 15. Cumulative Gain Error
LMH6521 30120171_nosb47.gif Figure 17. Noise Figure vs Frequency
LMH6521 30120188.gif Figure 19. Supply Current vs Temperature
LMH6521 30120199.gif Figure 21. Input Impedance
LMH6521 30120197_nosb47.gif Figure 2. Gain Flatness vs Temperature
LMH6521 30120176.gif Figure 4. OIP3 vs Temperature
LMH6521 30120183.gif Figure 6. Third Order Intermodulation Products
vs Frequency
LMH6521 30120181.gif Figure 8. Second Order Harmonic Distortion
vs Attenuation
LMH6521 30120189.gif Figure 10. Second Order Harmonic Distortion
vs Frequency
LMH6521 30120194.gif Figure 12. Third Order Harmonic Distortion
at 100 MHz
LMH6521 30120192.gif Figure 14. Third Order Harmonic Distortion
at 200 MHz
LMH6521 30120175.gif Figure 16. Cumulative Phase Shift
LMH6521 30120184.gif Figure 18. Noise Figure vs Attenuation
LMH6521 30120196.gif Figure 20. Channel-to-Channel Isolation
LMH6521 301201100.gif Figure 22. Output Impedance