The LMH6570 is a high performance analog multiplexer optimized for professional grade video and other high fidelity, high bandwidth analog applications. The output amplifier selects one of two buffered input signals based on the state of the SEL pin. The LMH6570 provides a 400 MHz bandwidth at 2-VPP output signal levels. Multimedia and high definition television (HDTV) applications can benefit from the 0.1-dB bandwidth of 150 MHz and the 2200-V/μs slew rate of LMH6570.
The LMH6570 supports composite video applications with its 0.02% and 0.05° differential gain and phase errors for NTSC and PAL video signals while driving a single, back terminated 75-Ω load. An 80-mA linear output current is available for driving multiple video load applications.
The LMH6570 gain is set by external feedback and gain set resistors for maximum flexibility.
The LMH6570 is available in the 8-pin SOIC package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMH6570 | SOIC (8) | 4.9 mm × 3.90 mm |
Changes from C Revision (May 2013) to D Revision
Changes from B Revision (April 2013) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | IN0 | I | Input Channel 0 |
2 | SEL | I | Select Pin |
3 | SD | I | Shutdown |
4 | IN1 | I | Input Channel 1 |
5 | V- | I | V- Supply |
6 | V+ | I | V+ Supply |
7 | OUT | O | Output |
8 | FB | I | Feedback |
SEL | SD | OUTPUT |
---|---|---|
1 | 0 | IN1 * (1+RF/RG) |
0 | 0 | IN0 * (1+RF/RG) |
X | 1 | Shutdown |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage (V+ − V−) | 13.2 | V | ||
IOUT(3) | 130 | mA | ||
Signal & Logic Input Pin Voltage | ±(VS + 0.6) | V | ||
Signal & Logic Input Pin Current | ±20 | mA | ||
Maximum Junction Temperature | +150 | °C | ||
Storage Temperature | −65 | +150 | °C | |
Soldering Information | Infrared or Convection (20 sec) | 235 | °C | |
Wave Soldering (10 sec) | 260 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Machine model (MM)(2) | ±200 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Operating Temperature | −40 | 85 | °C | ||
Supply Voltage | 6 | 12 | V |
THERMAL METRIC(1) | D | UNIT | |
---|---|---|---|
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 150 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 50 |
PARAMETER | TEST CONDITIONS(2) | MIN(4) | TYP(8) | MAX(4) | UNIT | ||
---|---|---|---|---|---|---|---|
FREQUENCY DOMAIN PERFORMANCE | |||||||
SSBW | −3 dB Bandwidth | VOUT = 0.5 VPP | 500 | MHz | |||
LSBW | –3 dB Bandwidth | VOUT = 2 VPP(5) | 400 | MHz | |||
.1 dBBW | 0.1 dB Bandwidth | VOUT = 0.25 VPP | 150 | MHz | |||
DG | Differential gain | RL = 150 Ω, f = 4.43 MHz | 0.02% | ||||
DP | Differential phase | RL = 150 Ω, f = 4.43 MHz | 0.05 | deg | |||
XTLK | Channel to channel crosstalk | All Hostile, f = 5 MHz | −70 | dBc | |||
TIME DOMAIN RESPONSE | |||||||
TRS | Channel to channel switching time | Logic transition to 90% output | 8 | ns | |||
Enable and disable times | Logic transition to 90% or 10% output. | 10 | ns | ||||
TRL | Rise and fall time | 4 V Step | 2.4 | ns | |||
TSS | Settling time to 0.05% | 2 V Step | 17 | ns | |||
OS | Overshoot | 2 V Step | 5% | ||||
SR | Slew rate | 4 V Step(5)(7) | 2200 | V/μs | |||
DISTORTION | |||||||
HD2 | 2nd Harmonic distortion | 2 VPP , 5 MHz | −68 | dBc | |||
HD3 | 3rd Harmonic distortion | 2 VPP , 5 MHz | −84 | dBc | |||
IMD | 3rd Order intermodulation products | 10 MHz, Two tones 2 Vpp at output | −80 | dBc | |||
EQUIVALENT INPUT NOISE | |||||||
VN | Voltage | >1 MHz, Input Referred | 5 | nV√HZ | |||
ICN | Current | >1 MHz, Input Referred | 5 | pA/√Hz | |||
STATIC, DC PERFORMANCE | |||||||
CHGM | Channel to channel gain difference | DC, Difference in gain between channels | ±0.005% | ±0.034% | |||
-40°C ≤ TJ ≤ 85°C | ±0.036% | ||||||
VIO | Input offset voltage | VIN = 0 V | 1 | ±15 | mV | ||
-40°C ≤ TJ ≤ 85°C | ±21 | ||||||
DVIO | Offset voltage drift(9) | 30 | µV/°C | ||||
IBN | Input bias current(6) | VIN = 0 V | −3 | ±8 | µA | ||
-40°C ≤ TJ ≤ 85°C | ±10 | ||||||
DIBN | Bias current drift(9) | 11 | nA/°C | ||||
IBI | Inverting input bias current(6) | Pin 8, Feedback point, VIN = 0 V |
−3 | ±18 | uA | ||
-40°C ≤ TJ ≤ 85°C | ±22 | ||||||
PSRR | Power supply rejection ratio |
DC, Input referred | 48 | 50 | dB | ||
-40°C ≤ TJ ≤ 85°C | 46 | ||||||
ICC | Supply current | No Load, Shutdown Pin (SD) > 0.8 V | 13.8 | 15 | mA | ||
-40°C ≤ TJ ≤ 85°C | 16 | ||||||
Supply current shutdown | Shutdown Pin (SD) > 2 V | 1.1 | 1.3 | mA | |||
-40°C ≤ TJ ≤ 85°C | 1.4 | ||||||
VIH | Logic high threshold | Select Pin & Shutdown pin (SEL, SD) | 2.0 | V | |||
VIL | Logic low threshold | Select Pin & Shutdown pin (SEL, SD) | 0.8 | V | |||
IiL | Logic pin input current low(6) | Logic Input = 0 V Select Pin & Shutdown Pin (SEL, SD) | −8 | −1 | µA | ||
-40°C ≤ TJ ≤ 85°C | -10 | ||||||
IiH | Logic pin input current high(6) | Logic Input = 5.0 V, Select Pin & Shutdown Pin (SEL, SD) | 57 | 68 | µA | ||
-40°C ≤ TJ ≤ 85°C | 75 | ||||||
MISCELLANEOUS PERFORMANCE | |||||||
RIN+ | Input resistance | 5 | kΩ | ||||
CIN | Input capacitance | 0.8 | pF | ||||
ROUT | Output resistance | Output Active, (SD < 0.8 V) | 0.04 | Ω | |||
ROUT | Output resistance | Output Disabled, (SD > 2 V) | 3000 | Ω | |||
COUT | Output capacitance | Output Disabled, (SD > 2 V) | 3.1 | pF | |||
VO | Output voltage range | No Load | ±3.51 | ±3.7 | V | ||
-40°C ≤ TJ ≤ 85°C | ±3.50 | ||||||
VOL | RL = 100 Ω | ±3.16 | ±3.5 | V | |||
-40°C ≤ TJ ≤ 85°C | ±3.15 | ||||||
CMIR | Input voltage range | ±2.5 | ±2.6 | V | |||
IO | Linear output current(6) | VIN = 0 V | +60 | ±80 | mA | ||
-70 | |||||||
-40°C ≤ TJ ≤ 85°C | ±55 | ||||||
ISC | Short circuit current(3) | VIN = ±2 V, Output shorted to ground | ±230 | mA |
PARAMETER | TEST CONDITIONS(2) | MIN(4) | TYP(8) | MAX(4) | UNIT | |
---|---|---|---|---|---|---|
FREQUENCY DOMAIN PERFORMANCE | ||||||
SSBW | −3 dB Bandwidth | VOUT = 0.5 VPP | 475 | MHz | ||
LSBW | −3 dB Bandwidth | VOUT = 2.0 VPP | 375 | MHz | ||
0.1 dBBW | 0.1 dB Bandwidth | VOUT = 0.5 VPP | 100 | MHz | ||
GFP | Peaking | DC to 200 MHz | 0.4 | dB | ||
XTLK | Channel to channel crosstalk | All Hostile, f = 5 MHz | −70 | dBc | ||
TIME DOMAIN RESPONSE | ||||||
TRL | Rise and Fall time | 2 V Step | 2 | ns | ||
TSS | Settling time to 0.05% | 2 V Step | 20 | ns | ||
OS | Overshoot | 2 V Step | 5% | |||
SR | Slew rate | 2 V Step | 1400 | V/μs | ||
DISTORTION | ||||||
HD2 | 2nd Harmonic distortion | 2 VPP, 10 MHz | −67 | dBc | ||
HD3 | 3rd Harmonic distortion | 2 VPP, 10 MHz | −87 | dBc | ||
STATIC, DC PERFORMANCE | ||||||
VIO | Input offset voltage | VIN = 0 V | 1 | mV | ||
IBN | Input bias current(6) | VIN = 0 V | -3 | μA | ||
PSRR | Power supply rejection ratio | DC, Input Referred | 49 | dB | ||
ICC | Supply current | No Load | 12.5 | mA | ||
VIH | Logic high threshold | Select Pin & Shutdown pin (SEL, SD), VIH ≊ V+ * 0.4 |
1.3 | V | ||
VIL | Logic low threshold | Select Pin & Shutdown pin (SEL, SD), VIL ≊ V+ * 0.12 |
0.4 | V | ||
MISCELLANEOUS PERFORMANCE | ||||||
RIN+ | Input resistance | 5 | kΩ | |||
CIN | Input capacitance | 0.8 | pF | |||
ROUT | Output resistance | 0.06 | Ω | |||
VO | Output voltage range | No Load | ±2 | V | ||
VOL | RL = 100 Ω | ±1.8 | V | |||
CMIR | Input voltage range | ±1.2 | V | |||
IO | Linear output current(3) | VIN = 0 V | ±60 | mA | ||
ISC | Short circuit current(3) | VIN = ±1 V, Output shorted to ground | ±150 | mA |
Positive value is current into device | ||
Positive value is current into device | ||
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LMH6570 is a high-speed 2:1 analog multiplexer, optimized for very high speed and low distortion. With selectable gain and excellent AC performance, the LMH6570 is ideally suited for switching high resolution, presentation grade video signals. The LMH6570 has no internal ground reference. Single or split supply configurations are both possible, however, all logic functions are referenced to the mid supply point. The LMH6570 features very high speed channel switching and disable times. When disabled the LMH6570 output is high impedance making MUX expansion possible by combining multiple devices. See Multiplexer Expansion. The LMH6570 SEL defaults to logic low (IN0 active). The default state for the SD pin is also logic low (device enabled). Both pins can be left floating if the default state is desired.
The LMH6570 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. Figure 25 shows a typical configuration for driving a 75-Ω cable. The output buffer is configured for a gain of 2, so using back terminated loads will give a net gain of 1.
The LMH6570 has a current feedback output buffer with gain determined by external feedback (RF) and gain set (RG) resistors. With current feedback amplifiers, the closed loop frequency response is a function of RF. For a gain of 2 V/V, the recommended value of RF is 576 Ω. For other gains, see Figure 26. Generally, lowering RF from the recommended value will peak the frequency response and extend the bandwidth while increasing the value of RF will cause the frequency response to roll off faster. Reducing the value of RF too far below the recommended value will cause overshoot, ringing and, eventually, oscillation.
Since all applications are slightly different, it is worth some experimentation to find the optimal RF for a given circuit. For more information see Current Feedback Loop Gain Analysis and Performance Enhancement, Application Note OA-13 (SNOA366), which describes the relationship between RF and closed-loop frequency response for current feedback operational amplifiers. The impedance looking into pin 8 is approximately 20 Ω. This allows for good bandwidth at gains up to 10 V/V. When used with gains over 10 V/V, the LMH6570 will exhibit a “gain bandwidth product” similar to a typical voltage feedback amplifier. For gains of over 10 V/V consider selecting a high performance video amplifier like the LMH6720 to provide additional gain.
It is possible to use multiple LMH6570 devices to expand the number of inputs that can be selected for output. Figure 27 shows a 4:1 MUX using two LMH6570 devices.
In such an application, the output settling may be longer than the LMH6570 switching specifications (~20 ns), while switching between two separate LMH6570 devices. The switching time limiting factor occurs when one LMH6570 is turned off and another one is turned on, using the SD (shutdown) pin. The output settling time consists of the time needed for the first LMH6570 to enter high impedance state plus the time required for the second LMH6570 output to dissipate left-over output charge of the first device (limited by the output current capability of the second device) and the time needed to settle to the final voltage value.
While Figure 27 MUX expansion benefits from more isolation, originating from the parasitic loading of the un-selected channels on the selected channel, afforded by individual ROUT on each multiplexer output, this configuration does not produce the fastest transition between individual LMH6570 devices. For fastest transition between LMH6570 devices, the configuration of Figure 28 can be used where the LMH6570 output pins are all shorted together.
Figure 29 shows typical transition waveforms and shows that SD pin switching settles in less than 145 ns.
If it is important in the end application to make sure that no two inputs are presented to the output at the same time, an optional delay block can be added, to drive the SHUTDOWN pin of each device. Figure 30 shows one possible approach to this delay circuit. The delay circuit shown will delay H to L transitions of SHUTDOWN (R1 and C1 decay) but will not delay its L to H transition. R2 should be kept small compared to R1 in order to not reduce the SHUTDOWN voltage and to produce little or no delay to SHUTDOWN.
With the SHUTDOWN pin putting the output stage into a high impedance state, several LMH6570 devices can be tied together to form a larger input MUX. However, there is a loading effect on the active output caused by the unselected devices. The circuit in Figure 31 shows how to compensate for this effect. For the 8:1 MUX function shown in Figure 31, the gain error would be about 0.7% or −0.06dB. In the circuit in Figure 31, resistor ratios have been adjusted to compensate for this gain error. By adjusting the gain of each multiplexer circuit the error can be reduced to the tolerance of the resistors used (1% in this example).
NOTE
Disabling of the LMH6570 using the EN pin is not recommended for use when doing multiplexer expansion. While disabled, If the voltage between the selected input and the chip output exceeds approximately 2 V the device will begin to enter a soft breakdown state. This will show up as reduced input to output isolation. The signal on the non-inverting input of the output driver amplifier will leak through to the inverting input, and then to the output through the feedback resistor. The worst case is a gain of 1 configuration where the non-inverting input follows the active input buffer and (through the feedback resistor) the inverting input follows the voltage driving the output stage. The solution for this is to use shutdown mode for multiplexer expansion.
The LMH6570 could support a dual antenna receiver with two physically separate antennas. Monitoring the signal strength of the active antenna and switching to the other antenna when a fade is detected is a simple way to achieve spacial diversity. This method gives about a 3 dB boost in average signal strength and is the least expensive method for combining signals.
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 32 shows the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Figure 33 gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values.
The LMH6570 is protected against electrostatic discharge (ESD) on all pins. The LMH6570 will survive 2000-V Human Body model and 200-V Machine model events. Under normal operation the ESD diodes have no effect on circuit performance. However, there are occasions when the ESD diodes will be evident. If the LMH6570 is driven by a large signal while the device is powered down, the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device. Therefore, it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation.
The LMH6570 is optimized for maximum speed and performance in the small form factor of the standard SOIC package. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation.
Follow these steps to determine the maximum power dissipation for the LMH6570:
where
where
The maximum power that t-he LMH6570 package can dissipate at a given temperature can be derived with the following equation:
where
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, whereas the smaller ceramic capacitors should be placed as close to the device as possible. In Figure 25, the capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.