SNOSAF2E February 2005 – May 2016 LMH6703
PRODUCTION DATA.
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VS | ±6.75 | V | |||
IOUT | See (2) | ||||
Common mode input voltage | V− | V+ | V | ||
Maximum junction temperature | 150 | °C | |||
Storage temperature | −65 | 150 | °C | ||
Soldering Information | Infrared or convection (20 sec.) | 235 | °C | ||
Wave soldering (10 sec.) | 260 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Machine model (MM), per JEDEC specification JESD22-C101, all pins(2) | ±200 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Operating temperature | –40 | 85 | °C | ||
Supply voltage | ±4 | ±6 | V |
THERMAL METRIC(1) | LMH6703 | UNIT | ||
---|---|---|---|---|
DBV (SOT-23) | D (SOIC) | |||
6 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 182 | 133 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 139 | 79 | °C/W |
RθJB | Junction-to-board thermal resistance | 40 | 73 | °C/W |
ψJT | Junction-to-top characterization parameter | 28 | 28 | °C/W |
ψJB | Junction-to-board characterization parameter | 40 | 73 | °C/W |
PARAMETER | CONDITIONS | MIN (4) | TYP (3) | MAX (4) | UNIT | |
---|---|---|---|---|---|---|
FREQUENCY DOMAIN PERFORMANCE | ||||||
SSBW | –3-dB bandwidth | VOUT = 0.5 VPP, AV = +1 | 1800 | MHz | ||
VOUT = 0.5 VPP, AV = +2 | 1200 | |||||
LSBW | VOUT = 2 VPP | 750 | ||||
VOUT = 4 VPP | 500 | |||||
GF | 0.1-dB gain flatness | VOUT = 0.5 VPP | 150 | MHz | ||
VOUT = 2 VPP | 150 | |||||
DG | Differential gain | RL = 150 Ω, 4.43 MHz | 0.01% | |||
DP | Differential phase | RL = 150 Ω, 4.43 MHz | 0.02 | deg | ||
TIME DOMAIN RESPONSE | ||||||
tr | Rise time | 2-V step, 10% to 90% | 0.5 | ns | ||
6-V step, 10% to 90% | 1.05 | ns | ||||
tf | Fall time | 2-V step, 10% to 90% | 0.5 | ns | ||
6-V step, 10% to 90% | 1.05 | ns | ||||
SR | Slew rate | 4-V step, 10% to 90% (2) | 4200 | V/µs | ||
6-V step, 10% to 90% (2) | 4500 | |||||
ts | Settling time | 2-V step, VOUT within 0.1% | 10 | ns | ||
DISTORTION AND NOISE RESPONSE | ||||||
HD2 | 2nd harmonic distortion | 2 VPP, 5 MHz, SOT-23-6 | −87 | dBc | ||
2 VPP, 20 MHz, SOT-23-6 | −69 | |||||
2 VPP, 50 MHz, SOT-23-6 | −60 | |||||
HD3 | 3rd harmonic distortion | 2 VPP, 5 MHz, SOT-23-6 | −100 | dBc | ||
2 VPP, 20 MHz, SOT-23-6 | −90 | |||||
2 VPP, 50 MHz, SOT-23-6 | −70 | |||||
IMD | 3rd order intermodulation products | 50 MHz, PO = 5 dBm/ tone | −80 | dBc | ||
en | Input referred voltage noise | >1 MHz | 2.3 | nV/√Hz | ||
in | Input referred noise current | Inverting Pin >1 MHz |
18.5 | pA/√Hz | ||
Input referred noise current | Non-Inverting Pin >1 MHz |
3 | pA/√Hz | |||
u | ||||||
VOS | Input offset voltage | ±1.5 | ±7 ±9 |
mV | ||
TCVOS | Input offset voltage average drift | (6) | 22 | µV/°C | ||
IB | Input bias current | Non-Inverting (5) | −7 | –20 –23 |
µA | |
Inverting (5) | −2 | ±35 ±44 |
||||
TCIB | Input bias current average drift | Non-Inverting (6) | +30 | nA/°C | ||
Inverting (6) | −70 | |||||
VO | Output voltage range | RL = ∞ | ±3.3 | ±3.45 | V | |
RL = 100 Ω | ±3.2 ±3.14 |
±3.4 | ||||
PSRR | Power supply rejection ratio | VS = ± 4.0 V to ±6.0 V | 48 46 |
52 | dB | |
CMRR | Common mode rejection ratio | VCM = −1.0 V to +1.0 V | 45 44 |
47 | dB | |
IS | Supply current (enabled) | SD = 2 V, RL = ∞ | 11 | 12.5 15.0 |
mA | |
Supply current (disabled) | SD = 0.8 V, RL = ∞ | 0.2 | 0.900 0.935 |
mA | ||
MISCELLANEOUS PERFORMANCE | ||||||
RIN+ | Non-inverting input resistance | 1 | MΩ | |||
RIN− | Inverting input resistance | Output Impedance of Input Buffer | 30 | Ω | ||
CIN | Non-inverting input capacitance | 0.8 | pF | |||
RO | Output resistance | Closed Loop | 0.05 | Ω | ||
CMVR | Input common mode voltage range | CMRR ≥ 40 dB | ±1.9 | V | ||
IO | Linear output current | VIN = 0 V, VOUT ≤ ±80 mV | ±55 | ±90 | mA | |
ENABLE/DISABLE PERFORMANCE (DISABLED LOW) | ||||||
TON | Enable time | 10 | ns | |||
TOFF | Disable time | 10 | ns | |||
Output glitch | 50 | mVPP | ||||
VIH | Enable voltage | SD ≥ VIH | 2.0 | V | ||
VIL | Disable voltage | SD ≤ VIL | 0.8 | V | ||
IIH | Disable pin bias current, high | SD = V+(5) | −7 | ±70 | µA | |
IIL | Disable pin bias current, low | SD = 0 V (5) | −50 | −240 | −400 | µA |
IOZ | Disabled output leakage current | VOUT = ±1.8 V | 0.07 | ±25 ±40 |
µA |