Table 1. Pins With Dual Functions

7.5.1.1 Parallel Interface

Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space dedicated to control lines. To place the LMH6881 into parallel mode the SPI pin (pin 5) is set to the logical zero state. Alternately the SPI pin can be connected directly to ground. The SPI pin has a weak internal resistor to ground. If left unconnected, the amplifier will operate in parallel mode.

In parallel mode the gain can be changed in 2-dB steps with a 4-bit gain control bus. The attenuator control pins are internally biased to logic high state with weak pull-up resistors, with the exception of D0 which is biased low due to the shared SDO function. If the control bus is left unconnected, the amplifier gain will be set to 6 dB. Table 2 shows the gain of the amplifier when controlled in parallel mode.

For fixed-gain applications the attenuator-control pins should be connected to the desired logic state instead of relying on the weak internal bias. Data from the gain-control pins directly drive the amplifier gain circuits. To minimize gain change glitches all gain pins should be driven with minimal skew. If gain-pin timing is uncertain, undesirable transients can be avoided by using the shutdown pin to disable the amplifier while the gain is changed. Gain glitches are most likely to occur when multiple bits change value for a small gain change, such as the gain change from 10 dB to 12 dB which requires changing all 4 gain-control pins.

A shutdown pin (SD == 0, amplifier on, SD == 1, amplifier off) is provided to reduce power consumption by disabling the highest power portions of the amplifier. The digital control circuit is not shut down and will preserve the last active gain setting during the disabled state. See the Typical Characteristics section for disable and enable timing information. The SD pin is functional in parallel mode only and disabled in serial mode.

Figure 39. Parallel Mode Connection

7.5.1.2 SPI-Compatible Serial Interface

The serial interface allows a great deal of flexibility in gain programming and reduced board complexity. The LMH6881 serial interface is a generic 4-wire synchronous interface that is compatible with SPI-type interfaces that are used on many microcontrollers and DSP controllers. Using only four wires, the SPI mode offers access to the 0.25-dB gain steps of the amplifier.

For systems where gain is changed only infrequently, or where only slower gain changes are required, serial mode is the best choice. To place the LMH6881 into serial mode the SPI pin (Pin 5) should be put into the logic high state. Alternatively the SPI pin can be connected directly to the 5-V supply bus. In this configuration the pins function as shown in Table 1. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out (SDO), and serial chip select (CS). The chip-select pin is active low meaning the device is selected when the pin is low.

The SD pin is inactive in the serial mode. This pin can be left disconnected for serial mode. The SPI interface has the ability to shut down the amplifier without using the SD pin.

The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the rising edge and to source the output data on the SDO pin on the falling edge. The user may disable clock and hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or disabled. The clock pulse-width minimum is equal to one setup plus one hold time, or 6 ns.

The CS pin is the chip-select pin. This pin is active low; the chip is selected in the logic low state. Each assertion starts a new register access - that is, the SDATA field protocol is required. The user is required to deassert this signal after the 16th clock. If the CS pin is deasserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted in and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the de-asserted pulse, which is specified in the Specifications section.

The SDI pin is the input pin for the serial data. Each write cycle is 16-bits long.

The SDO pin is the data output pin. This output is normally at a high impedance state, and is driven only when CS is asserted. Upon CS assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. The SDO pin is a current output and requires external bias resistor to develop the correct logic voltage. See Figure 41 for details on sizing the external bias resistor. Resistor values of 180 Ω to 400 Ω are recommended. The SDO pin can source 10 mA in the logic high state. With a bias resistor of 250 Ω the logic 1 voltage would be 2.5 V. In the logic 0 state, the SDO output is off and no current flows, so the bias resistor will pull the voltage to 0 V.

Each serial interface write access cycle is exactly 16 bits long as shown in Figure 40.

The external bias resistor means that in the high-impedance state the SDO pin impedance is equal to the external bias resistor value. If busing multiple SPI devices make sure that the SDO pins of the other devices can drive the bias resistor. The serial interface has four registers with address [0] to address [3]. Table 3 shows the content of each SPI register. Registers 0 and 1 are read only. Registers 2 and 3 are read/write and control the gain and power of the amplifier. Table 4 shows the data format of register 2 and Table 5 shows the data format of register 3.

Figure 40. Serial Interface Protocol (SPI Compatible)

Figure 41. Internal Operation of the SDO Pin