SNAS579G March 2012 – December 2014 LMK00105
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY ~ 1 to 3 pF) can affect the discrete load capacitor values, C1 and C2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:
Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1only:
Finally, solve for C1:
Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation.
The power dissipated in the crystal, PXTAL, can be computed by:
Where:
IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active.
As shown in Figure 19, an external resistor, RLIM, can be used to limit the crystal drive level if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 kΩ.
Figure 20 shows the LMK00105 output phase noise performance in crystal mode with the 25-MHz crystal specified in Table 5.