SNAS512J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2 Current Consumption and Power Dissipation Calculations

The current consumption values specified in Electrical Characteristics can be used to calculate the total power dissipation and IC power dissipation for any device configuration. Use Equation 6 to calculate the total VCC core supply current (ICC_TOTAL):

Equation 6. ICC_TOTAL = ICC_CORE + ICC_BANK_A + ICC_BANK_B + ICC_CMOS

where

  • ICC_CORE is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin).
  • ICC_BANK_A is the current for Bank A and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if disabled).
  • ICC_BANK_B is the current for Bank B and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if disabled).
  • ICC_CMOS is the current for the LVCMOS output (or 0 mA if REFout is disabled).

Since the output supplies (VCCOA, VCCOB, VCCOC) can be powered from 3 independent voltages, the respective output supply currents (ICCO_BANK_A, ICCO_BANK_B, ICCO_CMOS) should be calculated separately.

ICCO_BANK for either Bank A or B can be directly taken from the corresponding output supply current specification (ICCO_PECL, ICCO_LVDS, or ICCO_HCSL) provided the output loading matches the specified conditions. Otherwise, ICCO_BANK should be calculated as follows:

Equation 7. ICCO_BANK = IBANK_BIAS + (N × IOUT_LOAD)

where

  • IBANK_BIAS is the output bank bias current (fixed value).
  • IOUT_LOAD is the DC load current per loaded output pair.
  • N is the number of loaded output pairs in the bank (N = 0 to 5).

Table 11-1 shows the typical IBANK_BIAS values and IOUT_LOAD expressions for the three differential output types.

For LVPECL, it is possible to use a larger termination resistor (RT) to ground instead of terminating with 50 Ω to VTT = VCCO – 2 V; this technique is commonly used to eliminate the extra termination voltage supply (VTT) and potentially reduce device power dissipation at the expense of lower output swing. For example, when VCCO is 3.3 V, a RT value of 160 Ω to ground will eliminate the 1.3 V termination supply without sacrificing much output swing. In this case, the typical IOUT_LOAD is 25 mA, so ICCO_PECL for a fully-loaded bank reduces to 158 mA (versus 165 mA with 50-Ω resistors to VCCO – 2 V).

Table 11-1 Typical Output Bank Bias and Load Currents
CURRENT PARAMETERLVPECLLVDSHCSL
IBANK_BIAS33 mA34 mA6 mA
IOUT_LOAD(VOH - VTT)/RT + (VOL - VTT)/RT0 mA (No DC load current)VOH/RT

When the current consumption is calculated or known for each supply, the total power dissipation (PTOTAL) can be calculated as:

Equation 8. PTOTAL = (VCC × ICC_TOTAL) + (VCCOA × ICCO_BANK_A) + (VCCOB × ICCO_BANK_B) + (VCCOC × ICCO_CMOS)

If the device configuration has LVPECL or HCSL outputs, then it is also necessary to calculate the power dissipated in any termination resistors (PRT_ PECL and PRT_HCSL) and in any termination voltages (PVTT). The external power dissipation values can be calculated as follows:

Equation 9. PRT_PECL (per LVPECL pair) = (VOH - VTT)2/RT + (VOL - VTT)2/RT
Equation 10. PVTT_PECL (per LVPECL pair) = VTT * [(VOH - VTT)/RT + (VOL - VTT)/RT]
Equation 11. PRT_HCSL (per HCSL pair) = VOH2 / RT

Finally, the IC power dissipation (PDEVICE) can be computed by subtracting the external power dissipation values from PTOTAL as follows:

Equation 12. PDEVICE = PTOTAL – N1 × (PRT_PECL + PVTT_PECL) – N2 × PRT_HCSL

where

  • N1 is the number of LVPECL output pairs with termination resistors to VTT (usually Vcco - 2 V or GND).
  • N2 is the number of HCSL output pairs with termination resistors to GND.