SNAS512J
september 2011 – may 2023
LMK00301
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Parameter Measurement Information
8.1
Differential Voltage Measurement Terminology
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
VCC and VCCO Power Supplies
9.4
Device Functional Modes
9.4.1
Clock Inputs
9.4.2
Clock Outputs
9.4.2.1
Reference Output
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.1.1
Driving the Clock Inputs
10.2.1.2
Crystal Interface
10.2.2
Detailed Design Procedure
10.2.2.1
Termination and Use of Clock Drivers
10.2.2.1.1
Termination for DC Coupled Differential Operation
10.2.2.1.2
Termination for AC Coupled Differential Operation
10.2.2.1.3
Termination for Single-Ended Operation
10.2.3
Application Curves
11
Power Supply Recommendations
11.1
Power Supply Sequencing
11.2
Current Consumption and Power Dissipation Calculations
11.2.1
Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
11.2.2
Power Dissipation Example #2: Worst-Case Dissipation
11.3
Power Supply Bypassing
11.3.1
Power Supply Ripple Rejection
11.4
Thermal Management
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHS|48
MPQF159B
Thermal pad, mechanical data (Package|Pins)
RHS|48
QFND509A
Orderable Information
snas512j_oa
snas512j_pm
10.2.3
Application Curves
Figure 10-16
HCSL Phase Noise at 100 MHz