SNAS512J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-A8FD8D12-8800-4A23-BBB1-69AA6ADFCFB0-low.gif Figure 6-1 RHS Package48-Pin WQFNTop View
Table 6-1 Pin Functions(3)
PIN TYPE DESCRIPTION
NAME NO.
CLKin_SEL0 19 I Clock input selection pins (2)
CLKin_SEL1 22
CLKin0 20 I Universal clock input 0 (differential or single-ended)
CLKin0* 21
CLKin1 40 I Universal clock input 1 (differential or single-ended)
CLKin1* 40
CLKoutA_TYPE0 14 I Bank A output buffer type selection pins (2)
CLKoutA_TYPE1 47
CLKoutB_TYPE0 23 I Bank B output buffer type selection pins (2)
CLKoutB_TYPE1 39
CLKoutA0 1 O Differential clock output A0. Output type set by CLKoutA_TYPE pins.
CLKoutA0* 2
CLKoutA1 3 O Differential clock output A1. Output type set by CLKoutA_TYPE pins.
CLKoutA1* 4
CLKoutA2 6 O Differential clock output A2. Output type set by CLKoutA_TYPE pins.
CLKoutA2* 7
CLKoutA3 9 O Differential clock output A3. Output type set by CLKoutA_TYPE pins.
CLKoutA3* 10
CLKoutA4 11 O Differential clock output A4. Output type set by CLKoutA_TYPE pins.
CLKoutA4* 12
CLKoutB4* 25 O Differential clock output B4. Output type set by CLKoutB_TYPE pins.
CLKoutB4 26
CLKoutB3* 27 O Differential clock output B3. Output type set by CLKoutB_TYPE pins.
CLKoutB3 28
CLKoutB2* 30 O Differential clock output B2. Output type set by CLKoutB_TYPE pins.
CLKoutB2 31
CLKoutB1* 33 O Differential clock output B1. Output type set by CLKoutB_TYPE pins.
CLKoutB1 34
CLKoutB0* 35 O Differential clock output B0. Output type set by CLKoutB_TYPE pins.
CLKoutB0 36
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
GND 13, 18, 24, 37, 43, 48 GND Ground
NC 38 — Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in Absolute Maximum Ratings.
OSCin 16 I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
OSCout 17 O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
REFout 44 O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
REFout_EN 46 I REFout enable input. Enable signal is internally synchronized to selected clock input. (2)
VCC 15, 42 PWR Power supply for Core and Input Buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin.
VCCOA 5, 8 PWR Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
VCCOB 29, 32 PWR Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
VCCOC 45 PWR Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
(1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.
(2) CMOS control input with internal pull-down resistor.
(3) Any unused output pin should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, disabled, or set to Hi-Z, if possible. See Clock Outputs for output configuration and Termination and Use of Clock Drivers for output interface and termination techniques.