SNAS577G February 2012 – August 2018 LMK00304
PRODUCTION DATA.
TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|
CURRENT CONSUMPTION(2) | |||||||
ICC_CORE | Core Supply Current, All Outputs Disabled | CLKinX selected | 8.5 | 10.5 | mA | ||
OSCin selected | 10 | 13.5 | mA | ||||
ICC_PECL | Additive Core Supply Current, LVPECL Banks Enabled | 38 | 48 | mA | |||
ICC_LVDS | Additive Core Supply Current, LVDS Banks Enabled | 43 | 52 | mA | |||
ICC_HCSL | Additive Core Supply Current, HCSL Banks Enabled | 50 | 58.5 | mA | |||
ICC_CMOS | Additive Core Supply Current, LVCMOS Output Enabled | 3.5 | 5.5 | mA | |||
ICCO_PECL | Additive Output Supply Current, LVPECL Banks Enabled | Includes Output Bank Bias and Load Currents for both banks, RT = 50 Ω to Vcco – 2 V on all outputs | 135 | 163 | mA | ||
ICCO_LVDS | Additive Output Supply Current, LVDS Banks Enabled | 25 | 34.5 | mA | |||
ICCO_HCSL | Additive Output Supply Current, HCSL Banks Enabled | Includes Output Bank Bias and Load Currents for both banks, RT = 50 Ω on all outputs | 65 | 81.5 | mA | ||
ICCO_CMOS | Additive Output Supply Current, LVCMOS Output Enabled | 200 MHz, CL = 5 pF | Vcco = 3.3 V ± 5% | 9 | 10 | mA | |
Vcco = 2.5 V ± 5% | 7 | 8 | mA | ||||
POWER SUPPLY RIPPLE REJECTION (PSRR) | |||||||
PSRRPECL | Ripple-Induced
Phase Spur Level Differential LVPECL Output(3) |
100 kHz, 100 mVpp Ripple Injected on Vcco, Vcco = 2.5 V | 156.25 MHz | –65 | dBc | ||
312.5 MHz | –63 | ||||||
PSRRLVDS | Ripple-Induced Phase Spur Level Differential LVDS Output(3) | 156.25 MHz | –76 | dBc | |||
312.5 MHz | –74 | ||||||
PSRRHCSL | Ripple-Induced Phase Spur Level Differential HCSL Output(3) | 156.25 MHz | –72 | dBc | |||
312.5 MHz | –63 | ||||||
CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN) | |||||||
VIH | High-Level Input Voltage | 1.6 | Vcc | V | |||
VIL | Low-Level Input Voltage | GND | 0.4 | V | |||
IIH | High-Level Input Current | VIH = Vcc, Internal pulldown resistor | 50 | µA | |||
IIL | Low-Level Input Current | VIL = 0 V, Internal pulldown resistor | -5 | 0.1 | µA | ||
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) | |||||||
fCLKin | Input Frequency Range(10) | Functional up to 3.1 GHz
Output frequency range and timing specified per output type (refer to LVPECL, LVDS, HCSL, LVCMOS output specifications) |
DC | 3.1 | GHz | ||
VIHD | Differential Input High Voltage | CLKin driven differentially | Vcc | V | |||
VILD | Differential Input Low Voltage | GND | V | ||||
VID | Differential Input Voltage Swing(4) | 0.15 | 1.3 | V | |||
VCMD | Differential Input Common Mode Voltage | VID = 150 mV | 0.25 | Vcc – 1.2 | V | ||
VID = 350 mV | 0.25 | Vcc – 1.1 | |||||
VID = 800 mV | 0.25 | Vcc – 0.9 | |||||
VIH | Single-Ended Input High Voltage | CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM range | Vcc | V | |||
VIL | Single-Ended Input Low Voltage | GND | V | ||||
VI_SE | Single-Ended Input Voltage Swing(15)(17) | 0.3 | 2 | Vpp | |||
VCM | Single-Ended Input Common Mode Voltage | 0.25 | Vcc – 1.2 | V | |||
ISOMUX | Mux Isolation, CLKin0 to CLKin1 | fOFFSET > 50 kHz, PCLKinX = 0 dBm | fCLKin0 = 100 MHz | –84 | dBc | ||
fCLKin0 = 200 MHz | –82 | ||||||
fCLKin0 = 500 MHz | –71 | ||||||
fCLKin0 = 1000 MHz | –65 | ||||||
CRYSTAL INTERFACE (OSCin, OSCout) | |||||||
FCLK | External Clock Frequency Range(10) | OSCin driven single-ended, OSCout floating | 250 | MHz | |||
FXTAL | Crystal Frequency Range | Fundamental mode crystal
ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz) (5) |
10 | 40 | MHz | ||
CIN | OSCin Input Capacitance | 4 | pF | ||||
LVPECL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) | |||||||
fCLKout_FS | Maximum Output Frequency Full VOD Swing(10)(11) | VOD ≥ 600 mV,
RL = 100=Ω differential |
Vcco = 3.3 V ± 5%,
RT = 160 Ω to GND |
1.0 | 1.2 | GHz | |
Vcco = 2.5 V ± 5%,
RT = 91 Ω to GND |
0.75 | 1 | |||||
fCLKout_RS | Maximum Output Frequency
Reduced VOD Swing(10)(11) |
VOD ≥ 400 mV,
RL = 100-Ω differential |
Vcco = 3.3 V ± 5%,
RT = 160 Ω to GND |
1.5 | 3.1 | GHz | |
Vcco = 2.5 V ± 5%,
RT = 91 Ω to GND |
1.5 | 2.3 | |||||
JitterADD | Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz(10)(6)(16) | Vcco = 2.5 V ± 5%:
RT = 91 Ω to GND, Vcco = 3.3 V ± 5%: RT = 160 to GND, RL = 100-Ω differential |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
77 | 98 | fs | |
CLKin: 156.25 MHz,
Slew rate ≥ 3 V/ns |
54 | 78 | |||||
JitterADD | Additive RMS Jitter
Integration Bandwidth 1 MHz to 20 MHz(6) |
Vcco = 3.3 V,
RT = 160 Ω to GND, RL = 100-Ω differential |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
59 | fs | ||
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns |
64 | ||||||
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns |
30 | ||||||
JitterADD | Additive RMS Jitter with LVPECL clock source from LMK03806(6)(7) | Vcco = 3.3 V,
RT = 160 Ω to GND, RL = 100-Ω differential |
CLKin: 156.25 MHz, JSOURCE = 190 fs RMS (10 kHz to 1 MHz) | 20 | fs | ||
CLKin: 156.25 MHz, JSOURCE = 195 fs RMS (12 kHz to 20 MHz) | 51 | ||||||
Noise Floor | Noise Floor
fOFFSET ≥ 10 MHz(8)(9) |
Vcco = 3.3 V,
RT = 160 Ω to GND, RL = 100 Ω differential |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
–162.5 | dBc/Hz | ||
CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns | –158.1 | ||||||
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns |
–154.4 | ||||||
DUTY | Duty Cycle(10) | 50% input clock duty cycle | 45% | 55% | |||
VOH | Output High Voltage | TA = 25°C, DC Measurement,
RT = 50 Ω to Vcco - 2 V |
Vcco – 1.2 | Vcco – 0.9 | Vcco – 0.7 | V | |
VOL | Output Low Voltage | Vcco – 2 | Vcco – 1.75 | Vcco – 1.5 | V | ||
VOD | Output Voltage Swing(4) | 600 | 830 | 1000 | mV | ||
tR | Output Rise Time
20% to 80%(15) |
RT = 160 Ω to GND, Uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 100-Ω differential CL ≤ 5 pF | 175 | 300 | ps | ||
tF | Output Fall Time 80% to 20%(15) | 175 | 300 | ps | |||
LVDS OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) | |||||||
fCLKout_FS | Maximum Output Frequency Full VOD Swing (10)(11) | VOD ≥ 250 mV, RL = 100-Ω differential | 1.0 | 1.6 | GHz | ||
fCLKout_RS | Maximum Output Frequency
Reduced VOD Swing(10)(11) |
VOD ≥ 200 mV, RL = 100-Ω differential | 1.5 | 2.1 | GHz | ||
JitterADD | Additive RMS Jitter,
Integration Bandwidth 10 kHz to 20 MHz (10)(6)(16) |
RL = 100-Ω differential | CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
94 | 115 | fs | |
CLKin: 156.25 MHz,
Slew rate ≥ 3 V/ns |
70 | 90 | |||||
JitterADD | Additive RMS Jitter
Integration Bandwidth 1 MHz to 20 MHz(6) |
Vcco = 3.3 V,
RL = 100-Ω differential |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
89 | fs | ||
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns |
77 | ||||||
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns |
37 | ||||||
Noise Floor | Noise Floor
fOFFSET ≥ 10 MHz(8)(9) |
Vcco = 3.3 V,
RL = 100-Ω differential |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
–159.5 | dBc/Hz | ||
CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns | –157 | ||||||
CLKin: 625 MHz,
Slew rate ≥ 3 V/ns |
–152.7 | ||||||
DUTY | Duty Cycle(10) | 50% input clock duty cycle | 45% | 55% | |||
VOD | Output Voltage Swing(4) | TA = 25°C, DC Measurement, RL = 100-Ω differential | 250 | 400 | 450 | mV | |
ΔVOD | Change in Magnitude of VOD for Complementary Output States | –50 | 50 | mV | |||
VOS | Output Offset Voltage | 1.125 | 1.25 | 1.375 | V | ||
ΔVOS | Change in Magnitude of VOS for Complementary Output States | –35 | 35 | mV | |||
ISA
ISB |
Output Short Circuit Current Single Ended | TA = 25°C, Single-ended outputs shorted to GND | –24 | 24 | mA | ||
ISAB | Output Short Circuit Current Differential | Complementary outputs tied together | –12 | 12 | mA | ||
tR | Output Rise Time
20% to 80%(15) |
Uniform transmission line up to 10 inches with 50-Ω characteristic impedance,
RL = 100 Ω differential, CL ≤ 5 pF |
175 | 300 | ps | ||
tF | Output Fall Time
80% to 20%(15) |
175 | 300 | ps | |||
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) | |||||||
fCLKout | Output Frequency Range(10) | RL = 50 Ω to GND, CL ≤ 5 pF | DC | 400 | MHz | ||
JitterADD_PCIe | Additive RMS Phase Jitter for PCIe 3.0(10) | PCIe Gen 3,
PLL BW = 2–5 MHz, CDR = 10 MHz |
CLKin: 100 MHz,
Slew rate ≥ 0.6 V/ns |
0.03 | 0.15 | ps | |
JitterADD | Additive RMS Jitter
Integration Bandwidth 1 MHz to 20 MHz(6) |
Vcco = 3.3 V,
RT = 50 Ω to GND |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
77 | fs | ||
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns |
86 | ||||||
Noise Floor | Noise Floor
fOFFSET ≥ 10 MHz(8)(9) |
Vcco = 3.3 V,
RT = 50 Ω to GND |
CLKin: 100 MHz,
Slew rate ≥ 3 V/ns |
–161.3 | dBc/Hz | ||
CLKin: 156.25 MHz,
Slew rate ≥ 2.7 V/ns |
–156.3 | ||||||
DUTY | Duty Cycle(10) | 50% input clock duty cycle | 45% | 55% | |||
VOH | Output High Voltage | TA = 25°C, DC Measurement, RT = 50 Ω to GND | 520 | 810 | 920 | mV | |
VOL | Output Low Voltage | –150 | 0.5 | 150 | mV | ||
VCROSS | Absolute Crossing Voltage(10)(12) | RL = 50 Ω to GND, CL ≤ 5 pF | 250 | 350 | 460 | mV | |
ΔVCROSS | Total Variation of VCROSS(10)(12) | 140 | mV | ||||
tR | Output Rise Time
20% to 80%(15)(12) |
250 MHz, Unifrom transmission line up to 10 inches with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF | 300 | 500 | ps | ||
tF | Output Fall Time
80% to 20%(15)(12) |
300 | 500 | ps | |||
LVCMOS OUTPUT (REFout) | |||||||
fCLKout | Output Frequency Range(10) | CL ≤ 5 pF | DC | 250 | MHz | ||
JitterADD | Additive RMS Jitter
Integration Bandwidth 1 MHz to 20 MHz(6) |
Vcco = 3.3 V, CL ≤ 5 pF | 100 MHz, Input Slew rate ≥ 3 V/ns | 95 | fs | ||
Noise Floor | Noise Floor
fOFFSET ≥ 10 MHz(8)(9) |
Vcco = 3.3 V, CL ≤ 5 pF | 100 MHz, Input Slew rate ≥ 3 V/ns | –159.3 | dBc/Hz | ||
DUTY | Duty Cycle(10) | 50% input clock duty cycle | 45% | 55% | |||
VOH | Output High Voltage | 1-mA load | Vcco – 0.1 | V | |||
VOL | Output Low Voltage | 0.1 | V | ||||
IOH | Output High Current (Source) | Vo = Vcco / 2 | Vcco = 3.3 V | 28 | mA | ||
Vcco = 2.5 V | 20 | ||||||
IOL | Output Low Current (Sink) | Vcco = 3.3 V | 28 | mA | |||
Vcco = 2.5 V | 20 | ||||||
tR | Output Rise Time
20% to 80%(15)(12) |
250 MHz, Uniform transmission line up to 10 inches with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF | 225 | 400 | ps | ||
tF | Output Fall Time
80% to 20%(15)(12) |
225 | 400 | ps | |||
tEN | Output Enable Time(13) | CL ≤ 5 pF | 3 | cycles | |||
tDIS | Output Disable Time(13) | 3 | cycles | ||||
PROPAGATION DELAY and OUTPUT SKEW | |||||||
tPD_PECL | Propagation Delay
CLKin-to-LVPECL(15) |
RT = 160 Ω to GND, RL = 100-Ω differential,
CL ≤ 5 pF |
180 | 360 | 540 | ps | |
tPD_LVDS | Propagation Delay
CLKin-to-LVDS(15) |
RL = 100-Ω differential, CL ≤ 5 pF | 200 | 400 | 600 | ps | |
tPD_HCSL | Propagation Delay
CLKin-to-HCSL(15)(12) |
RT = 50 Ω to GND, CL ≤ 5 pF | 295 | 590 | 885 | ps | |
tPD_CMOS | Propagation Delay
CLKin-to-LVCMOS(15)(12) |
CL ≤ 5 pF | Vcco = 3.3 V | 900 | 1475 | 2300 | ps |
Vcco = 2.5 V | 1000 | 1550 | 2700 | ||||
tSK(O) | Output Skew
LVPECL/LVDS/HCSL (10)(12)(14) |
Skew specified between any two CLKouts with the same buffer type. Load conditions per output type are the same as propagation delay specifications. | 30 | 50 | ps | ||
tSK(PP) | Part-to-Part Output Skew
LVPECL/LVDS/HCSL (15)(12)(14) |
80 | 120 | ps |