SNAS577G February   2012  – August 2018 LMK00304

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      LVPECL Output Swing (VOD) vs. Frequency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
  9. 9 Application and Implementation
    1. 9.1 Driving the Clock Inputs
    2. 9.2 Crystal Interface
    3. 9.3 Termination and Use of Clock Drivers
      1. 9.3.1 Termination for DC-Coupled Differential Operation
      2. 9.3.2 Termination for AC-Coupled Differential Operation
      3. 9.3.3 Termination for Single-Ended Operation
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Current Consumption and Power Dissipation Calculations
      1. 10.2.1 Power Dissipation Example: Worst-Case Dissipation
    3. 10.3 Power Supply Bypassing
      1. 10.3.1 Power Supply Ripple Rejection
    4. 10.4 Thermal Management
      1. 10.4.1 Support for PCB Temperature up to 105°C
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3 Termination and Use of Clock Drivers

When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:

  • Transmission line theory should be followed for good impedance matching to prevent reflections.
  • Clock drivers should be presented with the proper loads.
    • LVDS outputs are current drivers and require a closed current loop.
    • HCSL drivers are switched current outputs and require a DC path to ground via 50 Ω termination.
    • LVPECL outputs are open emitter and require a DC path to ground.
  • Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level; in this case, the signal should normally be AC coupled.

It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the data sheet of the receiver or input being driven to determine the best termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode voltage).