SNAS578D February   2012  – March 2016 LMK00306

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VCC and VCCO Power Supplies
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
  9. 9 Application and Implementation
    1. 9.1 Driving the Clock Inputs
    2. 9.2 Crystal Interface
    3. 9.3 Termination and Use of Clock Drivers
      1. 9.3.1 Termination for DC Coupled Differential Operation
      2. 9.3.2 Termination for AC Coupled Differential Operation
      3. 9.3.3 Termination for Single-Ended Operation
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Current Consumption and Power Dissipation Calculations
      1. 10.2.1 Power Dissipation Example: Worst-Case Dissipation
    3. 10.3 Power Supply Bypassing
      1. 10.3.1 Power Supply Ripple Rejection
    4. 10.4 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
        1. 13.4 Thermal Management
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

36-Pin WQFN
Package NJK0036A
Top View
LMK00306 30177402.gif

Pin Functions(3)

PIN TYPE DESCRIPTION
NO. NAME
DAP DAP GND Die Attach Pad. Connect to the PCB ground plane for heat dissipation.
1, 19, 28 GND GND Ground
2, 5 VCCOA PWR Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
3, 4 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins.
6, 7 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins.
8, 9 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins.
10, 36 CLKoutA_TYPE0, CLKoutA_TYPE1 I Bank A output buffer type selection pins (2)
11, 32 Vcc PWR Power supply for Core and Input buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin.
12 OSCin I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock.
13 OSCout O Output for crystal. Leave OSCout floating if OSCin is driven by a single-ended clock.
14, 17 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (2)
15, 16 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended)
18, 29 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B output buffer type selection pins (2)
20, 21 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins.
22, 23 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins.
24, 27 VCCOB PWR Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
25, 26 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins.
30, 31 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended)
33 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high.
34 VCCOC PWR Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (1)
35 REFout_EN I REFout enable input. Enable signal is internally synchronized to selected clock input. (2)
(1) The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type.
(2) CMOS control input with internal pull-down resistor.
(3) Any unused output pins should be left floating with minimum copper length (see note in Clock Outputs), or properly terminated if connected to a transmission line, or disabled/Hi-Z if possible. See Clock Outputs for output configuration or Termination and Use of Clock Drivers for output interface and termination techniques.