SNAS635E December   2013  – January 2022 LMK00334

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements, Propagation Delay, and Output Skew
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Driving the Clock Inputs
        2. 9.2.1.2 Crystal Interface
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Termination and Use of Clock Drivers
        2. 9.2.2.2 Termination for DC-Coupled Differential Operation
        3. 9.2.2.3 Termination for AC-Coupled Differential Operation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Current Consumption and Power Dissipation Calculations
      1. 10.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 10.2 Power Supply Bypassing
      1. 10.2.1 Power Supply Ripple Rejection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Management
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise specified: VCC = 3.3 V ± 5%, VCCO = 3.3 V ± 5%, 2.5 V ± 5%, –40°C ≤ TA ≤ 85°C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent the most likely parametric norms at VCC = 3.3 V, VCCO = 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. (1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CURRENT CONSUMPTION (1)
ICC_CORECore supply current, all outputs disabledCLKinX selected8.510.5mA
OSCin selected1013.5mA
ICC_HCSL5058.5mA
ICC_CMOS3.55.5mA
ICCO_HCSLAdditive output supply current, HCSL banks enabledIncludes output bank bias and load currents for both banks, RT = 50 Ω on all outputs6581.5mA
ICCO_CMOSAdditive output supply current, LVCMOS output enabled200 MHz, CL = 5 pFVCCO = 3.3 V ±5%910mA
VCCO = 2.5V ± 5%78mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRRHCSLRipple-induced phase spur level(2)
Differential HCSL Output		156.25 MHz–72dBc
312.5 MHz–63
CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN)
VIHHigh-level input voltage1.6VCCV
VILLow-level input voltageGND0.4V
IIHHigh-level input currentVIH = VCC, internal pulldown resistor50μA
IILLow-level input currentVIL = 0 V, internal pulldown resistor–50.1μA
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)
fCLKinInput frequency range(8)Functional up to 400 MHz
Output frequency range and timing specified per output type (refer to LVCMOS output specifications)		DC400MHz
VIHDDifferential input high voltageCLKin driven differentiallyVccV
VILDDifferential input low voltageGNDV
VIDDifferential input voltage swing(3)0.151.3V
VCMDDifferential input CMD common-mode voltageVID = 150 mV0.25VCC – 1.2V
VID = 350 mV0.25VCC – 1.1
VID = 800 mV0.25VCC – 0.9
VIHSingle-ended input IH high voltageCLKinX driven single-ended (AC- or DC-coupled), CLKinX* AC-coupled to GND or externally biased within VCM rangeVCCV
VILSingle-ended input IL low voltageGNDV
VI_SESingle-ended input voltage swing(8)0.32Vpp
VCMSingle-ended input CM common-mode voltage0.25VCC – 1.2V
ISOMUXMux isolation, CLKin0 to CLKin1fOFFSET > 50 kHz, PCLKinX = 0 dBmfCLKin0 = 100 MHz–84dBc
fCLKin0 = 200 MHz–82
fCLKin0 = 500 MHz–71
fCLKin0 = 1000 MHz–65
CRYSTAL INTERFACE (OSCin, OSCout)
FCLKExternal clock frequency range(8)OSCin driven single-ended, OSCout floating250MHz
FXTALCrystal frequency rangeFundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)(4)1040MHz
CINOSCin input capacitance1pF
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKoutOutput frequency range(8)RL = 50 Ω to GND, CL ≤ 5 pFDC400MHz
JitterADD_PCleAdditive RMS phase jitter for PCIe 5.0(8)

PCIe Gen 5 filter

CLKin: 100 MHz, slew rate ≥ 0.5 V/ns0.015

0.03

ps

JitterADD_PCleAdditive RMS phase jitter for PCIe 4.0(8)PCIe Gen 4,
PLL BW = 2–5 MHz,
CDR = 10 MHz		CLKin: 100 MHz, slew rate ≥ 1.8 V/ns0.030.05ps
JitterADD_PCleAdditive RMS phase jitter for PCIe 3.0(8)PCIe Gen 3,
PLL BW = 2–5 MHz,
CDR = 10 MHz		CLKin: 100 MHz, slew rate ≥ 0.6 V/ns0.030.15ps
JitterADDAdditive RMS jitter integration bandwidth 12 MHz to 20 MHz(5)VCCO = 3.3 V,
RT = 50 Ω to GND		CLKin: 100 MHz, slew rate ≥ 3 V/ns77fs
Noise FloorNoise floor fOFFSET ≥ 10 MHz(6)(7)VCCO = 3.3 V,
RT = 50 Ω to GND		CLKin: 100 MHz, slew rate ≥ 3 V/ns–161.3dBc/Hz
DUTYDuty cycle(8)50% input clock duty cycle45%55%
VOHOutput high voltageTA = 25°C, DC measurement,
RT = 50 Ω to GND		520810920mV
–1500.5150mV
VOLOutput low voltage
VCROSSAbsolute crossing voltage(8)(9)RL = 50 Ω to GND, CL ≤ 5 pF250350460mV
140mV
ΔVCROSSTotal variation of VCROSS(8)(9)
tROutput rise time 20% to 80%(9)(12)250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF225400ps
tFOutput fall time 80% to 20%(9)(12)225400ps
LVCMOS OUTPUT (REFout)
fCLKoutOutput frequency range(8)CL ≤ 5 pFDC250MHz
JitterADDAdditive RMS jitter integration bandwidth 1 MHz to 20 MHz(5)VCCO = 3.3 V,
CL ≤ 5 pF		100 MHz, input slew rate ≥ 3 V/ns95fs
Noise FloorNoise floor fOFFSET ≥ 10 MHz(6)(7)VCCO = 3.3 V,
CL ≤ 5 pF		100 MHz, input slew rate ≥ 3 V/ns–159.3dBc/Hz
DUTYDuty cycle(8)50% input clock duty cycle45%55%
VOHOutput high voltage1-mA loadVCCO – 0.1V
VOLOutput low voltage0.1V
IOHOutput high current (source)VO = VCCO / 2VCCO = 3.3 V28mA
VCCO = 2.5 V20
VCCO = 3.3 V28mA
VCCO = 2.5 V20
IOLOutput low current (sink)
tROutput rise time 20% to 80%(9)(12)250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF225400ps
tFOutput fall time 80% to 20%(10)(12)225400ps
tENOutput enable time(10)CL ≤ 5 pF3cycles
tDISOutput disable time(10)3cycles
(1) See Section 10 and Section 11.3 for more information on current consumption and power dissipation calculations.
(2) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the VCCO supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10(PSRR / 20)) / (π × fCLK) ] × 1E12
(3) See Section 7.1 for definition of VID and VOD voltages.
(4) The ESR requirements stated must be met to ensure that the oscillator circuitry has no start-up issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 9.2.1.2 for crystal drive level considerations.
(5) For the 100-MHz and 156.25-MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625-MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2 × 10dBc/10) / (2 × π × fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 12-kHz to 20-MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10 × log10(20 MHz – 12 kHz).
(6) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations.
(7) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common-mode noise rejection. However, TI recommends using the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.
(8) Specification is ensured by characterization and is not tested in production.
(9) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
(10) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.
(11) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.
(12) Parameter is specified by design, not tested in production.