SNAS635E
December 2013 – January 2022
LMK00334
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements, Propagation Delay, and Output Skew
6.7
Typical Characteristics
7
Parameter Measurement Information
7.1
Differential Voltage Measurement Terminology
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Crystal Power Dissipation vs. RLIM
8.3.2
Clock Inputs
8.3.3
Clock Outputs
8.3.3.1
Reference Output
8.4
Device Functional Modes
8.4.1
VCC and VCCO Power Supplies
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Driving the Clock Inputs
9.2.1.2
Crystal Interface
9.2.2
Detailed Design Procedure
9.2.2.1
Termination and Use of Clock Drivers
9.2.2.2
Termination for DC-Coupled Differential Operation
9.2.2.3
Termination for AC-Coupled Differential Operation
9.2.3
Application Curve
10
Power Supply Recommendations
10.1
Current Consumption and Power Dissipation Calculations
10.1.1
Power Dissipation Example: Worst-Case Dissipation
10.2
Power Supply Bypassing
10.2.1
Power Supply Ripple Rejection
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
11.3
Thermal Management
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTV|32
MPQF166B
Thermal pad, mechanical data (Package|Pins)
RTV|32
QFND448B
Orderable Information
snas635e_oa
snas635e_pm
1
Features
3:1 Input multiplexer
Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
One crystal input accepts a 10- to 40-MHz crystal or single-ended clock
Two banks with two differential outputs each
HCSL, or Hi-Z (selectable)
Additive RMS phase jitter for PCIe Gen5 at 100 MHz:
15 fs RMS (typical)
High PSRR: –72 dBc at 156.25 MHz
LVCMOS output with synchronous enable input
Pin-controlled configuration
V
CC
core supply: 3.3 V ± 5%
Three independent V
CCO
output supplies: 3.3 V, 2.5 V ± 5%
Industrial temperature range: –40°C to +105°C
32-pin WQFN (5 mm × 5 mm)