SNAS636C December 2013 – July 2021 LMK00338
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CURRENT CONSUMPTION(3) | |||||||
ICC_CORE | Core supply current, all outputs disabled | CLKinX selected | 8.5 | 10.5 | mA | ||
OSCin selected | 10 | 13.5 | mA | ||||
ICC_HCSL | 31 | 38.5 | mA | ||||
ICC_CMOS | 3.5 | 5.5 | mA | ||||
ICCO_HCSL | Additive output supply current, HCSL banks enabled | Includes Output Bank Bias and Load Currents for both banks, RT = 50 Ω on all outputs in bank | 68 | 84 | mA | ||
ICCO_CMOS | Additive output supply current, LVCMOS output enabled | 200 MHz, CL = 5 pF |
VCCO = 3.3 V ±5% | 9 | 10 | mA | |
VCCO = 2.5V ± 5% | 7 | 8 | mA | ||||
POWER SUPPLY RIPPLE REJECTION (PSRR) | |||||||
PSRRHCSL | Ripple-induced phase spur level(4) Differential HCSL output |
156.25 MHz | –72 | dBc | |||
312.5 MHz | –63 | ||||||
CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN) | |||||||
VIH | High-level input voltage | 1.6 | Vcc | V | |||
VIL | Low-level input voltage | GND | 0.4 | V | |||
IIH | High-level input current | VIH = VCC, internal pulldown resistor | 50 | μA | |||
IIL | Low-level input current | VIL = 0 V, internal pulldown resistor | –5 | 0.1 | μA | ||
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) | |||||||
fCLKin | Input frequency range(10) | Functional up to 400 MHz Output frequency range and timing specified per output type (refer to HCSL, LVCMOS output specifications) |
DC | 400 | MHz | ||
VIHD | Differential input high voltage | CLKin driven differentially | VCC | V | |||
VILD | Differential input low voltage | GND | V | ||||
VID | Differential input voltage swing(5) | 0.15 | 1.3 | V | |||
VCMD | Differential input CMD common-mode voltage | VID = 150 mV | 0.25 | VCC – 1.2 | V | ||
VID = 350 mV | 0.25 | VCC – 1.1 | |||||
VID = 800 mV | 0.25 | VCC – 0.9 | |||||
VIH | Single-ended input IH high voltage | CLKinX driven single-ended (AC- or DC-coupled), CLKinX* AC-coupled to GND or externally biased within VCM range | VCC | V | |||
VIL | Single-ended input IL low voltage | GND | V | ||||
VI_SE | Single-ended input voltage swing(14) | 0.3 | 2 | Vpp | |||
VCM | Single-ended input CM common-mode voltage | 0.25 | VCC – 1.2 | V | |||
ISOMUX | Mux isolation, CLKin0 to CLKin1 | fOFFSET > 50 kHz, PCLKinX = 0 dBm |
fCLKin0 = 100 MHz | –84 | dBc | ||
fCLKin0 = 200 MHz | –82 | ||||||
fCLKin0 = 500 MHz | –71 | ||||||
fCLKin0 = 1000 MHz | –65 | ||||||
CRYSTAL INTERFACE (OSCin, OSCout) | |||||||
FCLK | External clock frequency range(10) | OSCin driven single-ended, OSCout floating | 250 | MHz | |||
FXTAL | Crystal frequency range | Fundamental mode crystal ESR ≤ 200 Ω (10 to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)(6) | 10 | 40 | MHz | ||
CIN | OSCin input capacitance | 1 | pF | ||||
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) | |||||||
fCLKout | Output frequency range(10) | RL = 50 Ω to GND, CL ≤ 5 pF | DC | 400 | MHz | ||
JitterADD_PCle | Additive RMS phase jitter for PCIe 5.0(10) | PCIe Gen 5 filter | CLKin: 100 MHz, Slew rate ≥ 0.5 V/ns |
0.015 |
0.03 |
ps |
|
JitterADD_PCle | Additive RMS phase jitter for PCIe 4.0(10) | PCIe Gen 4, PLL BW = 2–5 MHz, CDR = 10 MHz |
CLKin: 100 MHz, Slew rate ≥ 1.8 V/ns |
0.03 | 0.05 | ps | |
JitterADD_PCle | Additive RMS phase jitter for PCIe 3.0(10) | PCIe Gen 3, PLL BW = 2–5 MHz, CDR = 10 MHz |
CLKin: 100 MHz, Slew rate ≥ 0.6 V/ns |
0.03 | 0.15 | ps | |
JitterADD | Additive RMS jitter integration bandwidth to 20 MHz(8)(9) | VCCO = 3.3 V, RT = 50 Ω to GND |
CLKin: 100 MHz, Slew rate ≥ 3 V/ns |
77 | fs | ||
CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns |
86 | ||||||
Noise Floor | Noise floor fOFFSET ≥ 10 MHz(8)(9) | VCCO = 3.3 V, RT = 50 Ω to GND |
CLKin: 100 MHz, Slew rate ≥ 3 V/ns |
–161.3 | dBc/Hz | ||
CLKin: 156.25 MHz, Slew rate ≥ 2.7 V/ns |
–156.3 | ||||||
DUTY | Duty cycle(10) | 50% input clock duty cycle | 45% | 55% | |||
VOH | Output high voltage | TA = 25°C, DC measurement, RT = 50 Ω to GND |
520 | 810 | 920 | mV | |
–150 | 0.5 | 150 | mV | ||||
VOL | Output low voltage | ||||||
VCROSS | Absolute crossing voltage(10)(11) | RL = 50 Ω to GND, CL ≤ 5 pF |
160 | 350 | 460 | mV | |
140 | mV | ||||||
ΔVCROSS | Total variation of VCROSS | ||||||
tR | Output rise time 20% to 80%(11)(14) | 250 MHz, uniform transmission line up to
10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF |
300 | 500 | ps | ||
tF | Output fall time 80% to 20%(11)(14) | 300 | 500 | ps | |||
LVCMOS OUTPUT (REFout) | |||||||
fCLKout | Output frequency range(10) | CL ≤ 5 pF | DC | 250 | MHz | ||
JitterADD | Additive RMS jitter integration bandwidth 1 MHz to 20 MHz(7) | VCCO = 3.3 V, CL ≤ 5 pF |
100 MHz, Input slew rate ≥ 3 V/ns |
95 | fs | ||
Noise Floor | Noise floor fOFFSET ≥ 10 MHz(8)(9) | VCCO = 3.3 V, CL ≤ 5 pF |
100 MHz, Input slew rate ≥ 3 V/ns |
–159.3 | dBc/Hz | ||
DUTY | Duty cycle(10) | 50% input clock duty cycle | 45% | 55% | |||
VOH | Output high voltage | 1-mA load | VCCO – 0.1 | V | |||
VOL | Output low voltage | 0.1 | V | ||||
IOH | Output high current (source) | VO = VCCO / 2 | VCCO = 3.3 V | 28 | mA | ||
VCCO = 2.5 V | 20 | ||||||
VCCO = 3.3 V | 28 | mA | |||||
VCCO = 2.5 V | 20 | ||||||
IOL | Output low current (sink) | ||||||
tR | Output rise time 20% to 80%(11)(14) | 250 MHz, uniform transmission line up to 10 in. with 50-Ω characteristic impedance, RL = 50 Ω to GND, CL ≤ 5 pF | 225 | 400 | ps | ||
tF | Output fall time 80% to 20%(11)(14) | 225 | 400 | ps | |||
tEN | Output enable time(12) | CL ≤ 5 pF | 3 | cycles | |||
tDIS | Output disable time(12) | 3 | cycles | ||||
PROPAGATION DELAY and OUTPUT SKEW | |||||||
tPD_HCSL | Propagation delay CLKin-to-HCSL(11)(14) | RT = 50 Ω to GND, CL ≤ 5 pF |
295 | 590 | 885 | ps | |
tPD_CMOS | Propagation delay CLKin-to-LVCMOS(11)(14) | CL ≤ 5 pF | VCCO = 3.3 V | 900 | 1475 | 2300 | ps |
VCCO = 2.5 V | 1000 | 1550 | 2700 | ||||
tSK(O) | Output skew(10)(11)(13) | Skew specified between any two CLKouts.
Load conditions are the same as propagation delay specifications. |
30 | 50 | ps | ||
tSK(PP) | Part-to-part output skew HCSL(11)(14)(13) |
80 | 120 | ps |