SNAS784B March   2019  – August 2019 LMK00804B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Power Supply Characteristics
    6. Table 6. LVCMOS / LVTTL DC Electrical Characteristics
    7. Table 7. Differential Input DC Electrical Characteristics
    8. Table 8. Switching Characteristics
    9. Table 9. Pin Characteristics
    10. 6.1      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Enable Timing
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Output Clock Interface Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
          1. 9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
      2. 9.2.2 Input Detail
      3. 9.2.3 Input Clock Interface Circuits
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Power Dissipation Calculations
      2. 9.3.2 Thermal Management
      3. 9.3.3 Recommendations for Unused Input and Output Pins
      4. 9.3.4 Input Slew Rate Considerations
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
      1. 10.1.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Power Supply Pins
      3. 11.1.3 Differential Input Termination
      4. 11.1.4 LVCMOS Input Termination
      5. 11.1.5 Output Termination
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View

Pin Functions(2)

PIN TYPE(1) DESCRIPTION
NAME NO.
CLK_EN 4 I, PU Synchronous clock enable input. CLK_EN must be held low until a valid reference clock is provided. Typically connected to VDD with an external 1-kΩ pullup. When unused, leave floating.
0 = Outputs are forced to logic low state
1 = Outputs are enabled with LVCMOS/LVTTL levels
CLK_N 6 I, PD, PU Inverting differential clock input with internal 51-kΩ (typ) pullup resistor to VDD and internal 51-kΩ (typ) pulldown resistor to GND. Typically connected to the inverting clock input. When unused, leave floating. Internally biased to VDD/2 when left floating.
CLK_P 5 I, PD Noninverting differential clock input with internal 51-kΩ (typ) pulldown resistor to GND. Typically connected to the noninverting clock input. A single-ended clock input can also be connected to CLK_P. When unused, leave floating.
CLK_SEL 7 I, PU Clock select input. Typically connected to VDD with an external 1-kΩ pullup. When unused, leave floating.
0 = Select LVCMOS_CLK (pin 8)
1 = Select CLK_P, CLK_N (pins 5, 6)
GND 1, 9, 13 G Power supply ground.
LVCMOS_CLK 8 I, PD Single-ended clock input with internal 51-kΩ (typ) pulldown resistor to GND. Typically connected to a single-ended clock input. When unused, leave floating. Accepts LVCMOS/LVTTL levels.
NC 2 NC No connect pin. Typically left floating. Do not connect to GND.
Q0 16 O Single-ended clock outputs with LVCMOS/LVTTL levels at 7-Ω output impedance. Typically connected to a receiver with a 43-Ω series termination. When unused, leave floating.
Q1 14
Q2 12
Q3 10
VDD 3 P Power supply terminal. Typically connected to a 3.3-V supply. The VDD pin is typically connected GND with an external 0.1-uF capacitor.
VDDO 11, 15 P Output supply terminals. Typically connected to a 3.3-V, 2.5-V, 1.8-V, or 1.5-V supply. The VDDO pins are typically connected GND with external 0.1-uF capacitors.
(1) G = Ground, I = Input, O = Output, P = Power, PU = 51-kΩ pullup, PD = 51-kΩ pulldown. NC = No connect