SNAS784B March   2019  – August 2019 LMK00804B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Power Supply Characteristics
    6. Table 6. LVCMOS / LVTTL DC Electrical Characteristics
    7. Table 7. Differential Input DC Electrical Characteristics
    8. Table 8. Switching Characteristics
    9. Table 9. Pin Characteristics
    10. 6.1      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Enable Timing
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Output Clock Interface Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
          1. 9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
      2. 9.2.2 Input Detail
      3. 9.2.3 Input Clock Interface Circuits
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Power Dissipation Calculations
      2. 9.3.2 Thermal Management
      3. 9.3.3 Recommendations for Unused Input and Output Pins
      4. 9.3.4 Input Slew Rate Considerations
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
      1. 10.1.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Power Supply Pins
      3. 11.1.3 Differential Input Termination
      4. 11.1.4 LVCMOS Input Termination
      5. 11.1.5 Output Termination
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Power Dissipation Calculations

The following power considerations refer to the device-consumed power consumption only. The device power consumption is the sum of static and dynamic power. The dynamic power usage consists of two components:

  • Power used by the device as it switches states
  • Power required to charge any output load

The output load can be capacitive-only or capacitive and resistive. Use Equation 3 through Equation 5 to calculate the power consumption of the device:

Equation 3. PDev = Pstat + Pdyn + PCload
Equation 4. Pstat = (IDD × VDD) + (IDDO × VDDO)
Equation 5. Pdyn + PCload = (IDDO,dyn + IDDO,Cload) × VDDO

where

  • IDDO,dyn = CPD × VDDO × f × n [mA]
  • IDDO,Cload = Cload × VDDO × f × n [mA]

Example for power consumption of the LMK00804B-Q1: 4 outputs are switching, f = 100 MHz,

VDD = VDDO = 3.465 V and assuming Cload = 5 pF per output:

Equation 6. PDev = 90 mW + 34 mW = 124 mW
Equation 7. Pstat = (21 mA × 3.465 V) + (5 mA × 3.465 V) = 90 mW
Equation 8. Pdyn + PCload = (2.8 mA + 6.9 mA) × 3.465 V = 34 mW
Equation 9. IDD,dyn = 2 pF × 3.465 V × 100 MHz × 4 = 2.8 mA
Equation 10. IDD,Cload = 5 pF × 3.465 V × 100 MHz × 4 = 6.9 mA

NOTE

For dimensioning the power supply, consider the total power consumption. The total power consumption is the sum of device power consumption and the power consumption of the load.