SNAS573D January 2012 – September 2021 LMK01801
PRODUCTION DATA
CLKoutX_Y_DIV sets the divide value for the clock outputs X through Y. The divide may be even or odd. Both even and odd divides output a 50% duty cycle clock.
Programming CLKoutX_Y_DIV is as follows:
CLKoutX_Y_DIV | Programming Address |
---|---|
CLKout0_3_DIV | R5[6:4] |
CLKout4_7_DIV | R5[9:7] |
CLKout8_11_DIV | R5[12:10] |
CLKout12_13_DIV | R5[27:17] |
R5[12:10, 9:7, 6:4] | Divide Value |
---|---|
0 (0x00) | 8 |
1 (0x01) | 1 |
2 (0x02) | 2 |
3 (0x03) | 3 |
4 (0x04) | 4 |
5 (0x05) | 5 |
6 (0x06) | 6 |
7 (0x07) | 7 |
R5[27:17] | Divide Value | Power Mode |
---|---|---|
0 (0x00) | Invalid | Normal Mode |
1 (0x01) | 1 | |
2 (0x02) | 2(1) | |
3 (0x03) | 3 | |
4 (0x04) | 4 (1) | |
5 (0x05) | 5 (1) | |
6 (0x06) | 6 | |
... | ... | |
24 (0x18) | 24 | |
25 (0x19) | 25 | |
26 (0x1A) | 26 | Extended Mode |
27 (0x1B) | 27 | |
... | ... | |
1044 (0x414) | 1044 | |
1045 (0x415) | 1045 |
Using a divide value of 26 or greater will cause the clock group to operate in extended mode regardless of the clock group’s digital delay value.