SNAS573 Data sheet

SNAS573D January 2012 – September 2021 LMK01801

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RHS|48
- MPQF159B

Thermal pad, mechanical data (Package|Pins)

RHS|48
- QFND509A

Orderable Information

7.4 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, –40°C ≤ T_A ≤ 85°C. Typical values represent most likely parametric norms at V_CC = 3.3 V, T_A = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not ensured.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{CC_PD}	Power Down Supply Current			1		mA
I_{CC_CLKS}	Supply Current with all clocks enabled ⁽²⁾	All clock delays disabled, CLKoutX_Y_DIV = 1, CLKoutX_TYPE = 1 (LVDS),		313	390	mA
CLKin0/0* AND CLKin1/1* INPUT CLOCK SPECIFICATIONS
f_CLKinX	Clock 0 or 1 Input Frequency	CLKinX_MUX = Bypassed CLKoutX_Y_DIV = 1	0.001		3100	MHz
		CLKinX_MUX = Bypassed CLKoutX_Y_DIV = 2 to 8	0.001		1600	MHz
		CLKin_MUX = Divide CLKinX_DIV = 2 to 8	0.001		3100	MHz
SLEW_CLKin	Slew Rate on CLKin ⁽³⁾	20% to 80%	0.15	0.5		V/ns
DUTY_CLKin	Clock input duty cycle			50%
V_CLKin	Clock Input, Single-ended Input Voltage	AC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_BUF_TYPE = Bipolar	0.25		2.4	Vpp
V_CLKin	Clock Input, Single-ended Input Voltage	AC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_BUF_TYPE = MOS	0.25		2.4	Vpp
V_IDCLK_in	Clock Input Differential Input Voltage ⁽¹⁾⁽⁹⁾	AC coupled (CLKinX_BUF_TYPE = Bipolar	0.25		1.55	\|V\|
V_SSCLK_in		AC coupled (CLKinX_BUF_TYPE = Bipolar	0.5		3.1	Vpp
V_IDCLK_in		AC coupled (CLKinX_BUF_TYPE = MOS	0.25		1.55	\|V\|
V_SSCLK_in		AC coupled (CLKinX_BUF_TYPE = MOS	0.5		3.1	Vpp
V_{CLKinX-offset}	DC offset voltage between CLKinX/CLKinX* CLKinX* - CLKinX	Each pin AC coupled CLKinX_BUF_TYPE = Bipolar		0		mV
V_{CLKinX-offset}	DC offset voltage between CLKinX/CLKinX* CLKinX* - CLKinX	Each pin AC coupled CLKinX_BUF_TYPE = Bipolar		0		mV
V_CLKin- V_IH	Maximum input voltage	DC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = MOS	2.0		V_CC	V
V_CLKin- V_IL	Minimum input voltage		0.0		0.4	V
V_{CLKinX-offset}	DC offset voltage between CLKinX/CLKinX* CLKinX* - CLKinX	Each pin AC coupled CLKinX_BUF_TYPE = MOS		55		mV
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire) for EN_PIN_CTRL = MIDDLE
V_IH	High-Level Input Voltage		1.2		V_CC	V
V_IL	Low-Level Input Voltage				0.4	V
I_IH	High-Level Input Current	V_IH = V_CC	-5		5	µA
I_IL	Low-Level Input Current	V_IL = 0	-5		5	µA
DIGITAL INPUTS (SYNC0, SYNC1) FOR EN_PIN_CTRL = MIDDLE
V_IH	High-Level Input Voltage		1.2		V_CC	V
V_IL	Low-Level Input Voltage				0.4	V
I_IH	High-Level Input Current V_IH = V_CC	V_IH = V_CC	-5		5	µA
I_IL	Low-Level Input Current V_IL = 0 V	V_IL = 0	-40		-5	µA
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire, SYNC0, SYNC1) FOR EN_PIN_CTRL= LOW OR HIGH
V_IH	High-Level Input Voltage		2.6		V_CC	V
V_IM	Mid-Level Input Voltage		1.3		1.85	V
V_IL	Low-Level Input Voltage				0.7	V
I_IH	High-Level Input Current	V_IH = V_CC			100	µA
I_IM	Mid-Level Input Current		-10		10	µA
I_IL	Low-Level Input Current	V_IL= 0	-100			µA
CLOCK SKEW AND DELAY
T_PD	CLKinX to CLKoutY	Single-ended CLKinX* input, LVDS output		2.25		ns
T_SKEW	CLKoutX to CLKoutY ⁽⁴⁾⁽⁵⁾	LVDS-to-LVDS, T = 25°C, F_CLK = 800 MHz, R_L= 100 Ω AC coupled, Within same Divider		3		ps
	CLKoutX to CLKoutY ⁽⁴⁾⁽⁵⁾	LVPECL-to-LVPECL, T = 25°C F_CLK = 800 MHz, R_L= 100 Ω emitter resistors = 240 Ω to GND AC coupled, Within same Divider		3
	Skew between any two LVCMOS outputs, same CLKout or different CLKout ⁽⁴⁾⁽⁵⁾	R_L = 50 Ω, C_L = 10 pF, T = 25 °C, F_CLK = 100 MHz, Within same Divider		50
MixedT_SKEW CLKoutX - CLKoutY	LVPECL to LVDS skew	Same device, T = 25°C, 250 MHz, Within same Divider		32		ps
	LVDS to LVCMOS skew			830
	LVCMOS to LVPECL skew			800
F_ADLY	Maximum Analog Delay Frequency		1536			MHz
LVDS CLOCK OUTPUTS (CLKoutX)
f_CLKout	Maximum Clock Frequency ⁽⁵⁾⁽⁶⁾	R_L = 100 Ω	1600			MHz
V_OD	Differential Output Voltage ⁽¹⁾⁽⁹⁾	T = 25°C, DC measurement AC coupled to receiver input R = 100 Ω differential termination	225	400	575	mV
ΔV_OD	Change in Magnitude of V_OD for complementary output states		-50		50	mV
V_OS	Output Offset Voltage		1.125	1.25	1.375	V
ΔV_OS	Change in V_OS for complementary output states				35	\|mV\|
T_R	Output Rise Time	20% to 80%, R_L = 100 Ω		200		ps
T_F	Output Fall Time	80% to 20%, R_L = 100 Ω		300		ps
I_SA I_SB	Output short circuit current - single ended	Single-ended output shorted to GND, T = 25°C	-24		24	mA
I_SAB	Output short circuit current - differential	Complimentary outputs tied together	-12		12	mA
LVPECL CLOCK OUTPUTS (CLKoutX)
T_R	Output Rise Time	20% to 80%, R_L = 100 Ω, emitter resistors = 240 Ω to GND		200		ps
T_F	Output Fall Time	80% to 20%, R_L = 100 Ω, emitter resistors = 240 Ω to GND		200		ps
LOW COMMON-MODE VOLTAGE PECL (LCPECL)⁽⁷⁾, ⁽⁸⁾
f_CLKout	Maximum Clock Frequency ⁽⁵⁾⁽⁶⁾	R_L = 100 Ω, emitter resistors = 240 Ω to GND	3100			MHz
V_OH	Output High Voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC - 0.6 V		1.6		V
V_OL	Output Low Voltage			0.75		V
V_OD	Output Voltage		535	840	1145	mV
1600-mV LVPECL (LVPECL) CLOCK OUTPUTS (CLKoutX)
f_CLKout	Maximum Clock Frequency ⁽⁵⁾⁽⁶⁾	R_L = 100 Ω, emitter resistors = 240 Ω to GND	3100			MHz
V_OH	Output High Voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC - 2.0 V		V_CC - 0.94		V
V_OL	Output Low Voltage			V_CC - 1.9		V
V_OD	Output Voltage		585	925	1240	mV
2000-mV LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX)
f_CLKout	Maximum Clock Frequency ⁽⁵⁾⁽⁶⁾	R_L = 100 Ω, emitter resistors = 240 Ω to GND	3100			MHz
V_OH	Output High Voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC - 2.3 V		V_CC - 0.97		V
V_OL	Output Low Voltage			V_CC - 1.95		V
V_OD	Output Voltage		705	1150	1585	mV
LVCMOS CLOCK OUTPUTS (CLKoutX)
f_CLKout	Maximum Clock Frequency ⁽⁵⁾⁽⁶⁾	5-pF Load	250			MHz
V_OH	Output High Voltage	1-mA Load	V_CC - 0.1			V
V_OL	Output Low Voltage	1-mA Load			0.1	V
I_OH	Output High Current (Source)	V_CC = 3.3 V, V_O = 1.65 V		28		mA
I_OL	Output Low Current (Sink)	V_CC = 3.3 V, V_O = 1.65 V		28		mA
DUTY_CLK	Output Duty Cycle ⁽⁵⁾	V_CC/2 to V_CC/2, F_CLK = 100 MHz, T = 25 °C	45%	50%	55%
T_R	Output Rise Time	20% to 80%, R_L = 50 Ω, C_L = 5 pF		400		ps
T_F	Output Fall Time	80% to 20%, R_L = 50 Ω, C_L = 5 pF		400		ps
MICROWIRE INTERFACE TIMING
T_ECS	LE to Clock Set Up Time	See MICROWIRE Input Timing	25			ns
T_DCS	Data to Clock Set Up Time	See MICROWIRE Input Timing	25			ns
T_CDH	Clock to Data Hold Time	See MICROWIRE Input Timing	8			ns
T_CWH	Clock Pulse Width High	See MICROWIRE Input Timing	25			ns
T_CWL	Clock Pulse Width Low	See MICROWIRE Input Timing	25			ns
T_CES	Clock to LE Set Up Time	See MICROWIRE Input Timing	25			ns
T_EWH	LE Pulse Width	See MICROWIRE Input Timing	25			ns

(1) See applications section Section 8.1 for definition of V_ID and V_OD voltages.

(2) For Icc for specific part configuration, see applications section Section 11.1 for calculating Icc.

(3) The minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(4) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.

(5) Ensured by characterization.

(6) Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.

(7) For LCPECL, the common mode voltage is regulated (VOH=1.6V, VOL=VOH-Vsw, Vcm=(VOH+VOL)/2 ) and is more stable against with PVT (process, supply, temperature) variations than conventional LVPECL implementations..

(8) With proper selection of external emitter resistors, LCPECL can also be used for DC-coupling with devices with low common voltage such as 0.5V or 0.8V etc.

(9) Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for more information.