SNAS573D
January 2012 – September 2021
LMK01801
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
5.1
Functional Configurations
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Recommended Operating Conditions
7.3
Thermal Information
7.4
Electrical Characteristics
7.5
Serial MICROWIRE Timing Diagram
7.6
Typical Characteristics
8
Parameter Measurement Information
8.1
Differential Voltage Measurement Terminology
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
High-Speed Clock Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
9.3.2
Clock Distribution
9.3.3
Small Divider (1 to 8)
9.3.4
Large Divider (1 to 1045)
9.3.5
CLKout Analog Delay
9.3.6
CLKout0 to CLKout11 Digital Delay
9.3.7
CLKout12 and CLKout13 Digital Delay
9.3.8
Programmable Outputs
9.3.9
Clock Output Synchronization
9.3.10
Default Clock Outputs
9.4
Device Functional Modes
9.4.1
Programmable Mode
9.4.2
Pin Control Mode
9.4.3
Inputs / Outputs
9.4.3.1
CLKin0 and CLKin1
9.4.4
Input and Output Dividers
9.4.5
Fixed Digital Delay
9.4.5.1
Fixed Digital Delay - Example
9.4.6
Clock Output Synchronization (SYNC)
9.4.6.1
Dynamically Programming Digital Delay
9.4.6.1.1
Relative Dynamic Digital Delay
9.4.6.1.2
Relative Dynamic Digital Delay - Example
9.5
Programming
9.5.1
Recommended Programming Sequence
9.5.1.1
Overview
9.6
Register Map
9.6.1
Default Device Register Settings After Power On/Reset
9.6.2
Register R0
9.6.2.1
RESET
9.6.2.2
POWERDOWN
9.6.2.3
CLKoutX_Y_PD
9.6.2.3.1
CLKinX_BUF_TYPE
9.6.2.3.2
CLKinX_DIV
9.6.2.3.3
CLKinX_MUX
9.6.3
Register R1 and R2
9.6.3.1
CLKoutX_TYPE
9.6.4
Register R3
9.6.4.1
CLKout12_13_ADLY
9.6.4.2
CLKout12_13_HS, Digital Delay Half Shift
9.6.4.3
SYNC1_QUAL
9.6.4.4
SYNCX_POL_INV
9.6.4.5
NO_SYNC_CLKoutX_Y
9.6.4.6
CLKoutX_Y_OFFSET_PD
9.6.4.7
SYNCX_FAST
9.6.4.8
SYNCX_AUTO
9.6.5
Register R4
9.6.5.1
CLKout12_13_DDLY, Clock Channel Digital Delay
9.6.6
Register R5
9.6.6.1
CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay
9.6.6.2
CLKoutX_Y_DIV Clock Output Divide
9.6.7
Register 15
9.6.7.1
uWireLock
10
Application and Implementation
10.1
Typical Application
10.1.1
Detailed Design Procedure
10.1.1.1
Driving CLKin Inputs
10.1.1.1.1
Driving CLKin Pins With a Differential Source
10.1.1.1.2
Driving CLKin Pins With a Single-Ended Source
10.1.1.2
Termination and Use of Clock Output (Drivers)
10.1.1.2.1
Termination for DC-Coupled Differential Operation
10.1.1.2.2
Termination for AC-Coupled Differential Operation
10.1.1.2.3
Termination for Single-Ended Operation
11
Power Supply Recommendations
11.1
Current Consumption
12
Layout
12.1
Layout Guidelines
12.1.1
Pin Connection Recommendations
12.1.1.1
Vcc Pins and Decoupling
12.1.1.2
Unused clock outputs
12.1.1.3
Unused clock inputs
12.1.1.4
Unused GPIO (CLKoutTYPE_X)
12.1.1.5
Bias
12.1.1.6
In MICROWIRE Mode
12.2
Thermal Management
13
Device and Documentation Support
13.1
Documentation Support
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RHS|48
MPQF159B
Thermal pad, mechanical data (Package|Pins)
RHS|48
QFND509A
Orderable Information
snas573d_oa
snas573d_pm
10.1.1
Detailed Design Procedure