SNAS573D January   2012  – September 2021 LMK01801

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Functional Configurations
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Serial MICROWIRE Timing Diagram
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  High-Speed Clock Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
      2. 9.3.2  Clock Distribution
      3. 9.3.3  Small Divider (1 to 8)
      4. 9.3.4  Large Divider (1 to 1045)
      5. 9.3.5  CLKout Analog Delay
      6. 9.3.6  CLKout0 to CLKout11 Digital Delay
      7. 9.3.7  CLKout12 and CLKout13 Digital Delay
      8. 9.3.8  Programmable Outputs
      9. 9.3.9  Clock Output Synchronization
      10. 9.3.10 Default Clock Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Programmable Mode
      2. 9.4.2 Pin Control Mode
      3. 9.4.3 Inputs / Outputs
        1. 9.4.3.1 CLKin0 and CLKin1
      4. 9.4.4 Input and Output Dividers
      5. 9.4.5 Fixed Digital Delay
        1. 9.4.5.1 Fixed Digital Delay - Example
      6. 9.4.6 Clock Output Synchronization (SYNC)
        1. 9.4.6.1 Dynamically Programming Digital Delay
          1. 9.4.6.1.1 Relative Dynamic Digital Delay
          2. 9.4.6.1.2 Relative Dynamic Digital Delay - Example
    5. 9.5 Programming
      1. 9.5.1 Recommended Programming Sequence
        1. 9.5.1.1 Overview
    6. 9.6 Register Map
      1. 9.6.1 Default Device Register Settings After Power On/Reset
      2. 9.6.2 Register R0
        1. 9.6.2.1 RESET
        2. 9.6.2.2 POWERDOWN
        3. 9.6.2.3 CLKoutX_Y_PD
          1. 9.6.2.3.1 CLKinX_BUF_TYPE
          2. 9.6.2.3.2 CLKinX_DIV
          3. 9.6.2.3.3 CLKinX_MUX
      3. 9.6.3 Register R1 and R2
        1. 9.6.3.1 CLKoutX_TYPE
      4. 9.6.4 Register R3
        1. 9.6.4.1 CLKout12_13_ADLY
        2. 9.6.4.2 CLKout12_13_HS, Digital Delay Half Shift
        3. 9.6.4.3 SYNC1_QUAL
        4. 9.6.4.4 SYNCX_POL_INV
        5. 9.6.4.5 NO_SYNC_CLKoutX_Y
        6. 9.6.4.6 CLKoutX_Y_OFFSET_PD
        7. 9.6.4.7 SYNCX_FAST
        8. 9.6.4.8 SYNCX_AUTO
      5. 9.6.5 Register R4
        1. 9.6.5.1 CLKout12_13_DDLY, Clock Channel Digital Delay
      6. 9.6.6 Register R5
        1. 9.6.6.1 CLKout12_ADLY_SEL[13], CLKout13_ADLY_SEL[14], Select Analog Delay
        2. 9.6.6.2 CLKoutX_Y_DIV Clock Output Divide
      7. 9.6.7 Register 15
        1. 9.6.7.1 uWireLock
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Detailed Design Procedure
        1. 10.1.1.1 Driving CLKin Inputs
          1. 10.1.1.1.1 Driving CLKin Pins With a Differential Source
          2. 10.1.1.1.2 Driving CLKin Pins With a Single-Ended Source
        2. 10.1.1.2 Termination and Use of Clock Output (Drivers)
          1. 10.1.1.2.1 Termination for DC-Coupled Differential Operation
          2. 10.1.1.2.2 Termination for AC-Coupled Differential Operation
          3. 10.1.1.2.3 Termination for Single-Ended Operation
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pin Connection Recommendations
        1. 12.1.1.1 Vcc Pins and Decoupling
        2. 12.1.1.2 Unused clock outputs
        3. 12.1.1.3 Unused clock inputs
        4. 12.1.1.4 Unused GPIO (CLKoutTYPE_X)
        5. 12.1.1.5 Bias
        6. 12.1.1.6 In MICROWIRE Mode
    2. 12.2 Thermal Management
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.1 Default Device Register Settings After Power On/Reset

The Default Device Register Settings after Power On/Reset Table below illustrates the default register settings programmed in silicon for the LMK018xx after power on or asserting the reset bit. Capital X and Y represent numeric values.

Table 9-8 Default Device Register Settings After Power On/Reset
FIELD NAME DEFAULT VALUE (DECIMAL) DEFAULT STATE FIELD DESCRIPTION REGISTER BIT LOCATION (MSB:LSB)
RESET 0 Not in reset Performs power on reset for device R0 4
POWERDOWN 0 Disabled (device is active) Device power down control R0 5
CLKout0_3_PD 0 Disabled Power down the divider and clock outputs 0 through 3 R0 6
CLKout4_7_PD 0 Disabled Power down the divider and clock outputs 4 through 7 R0 7
CLKout8_11_PD 0 Disabled Power down the divider and clock outputs 8 through 11 R0 8
CLKout12_13_PD 0 Disabled Power down the divider and clock outputs 12 through 13 R0 9
CLKin0_BUF_TYPE 0 Bipolar Clock in buffer type R0 10
CLKin1_BUF_TYPE 0 Bipolar Clock in buffer type R0 11
CLKin0_DIV 2 Divide by 2 Divider value for CLKin0 R0 14:16 [3]
CLKin0_MUX 0 Bypass Enables or bypasses the CLKin0 divider R0 17:18 [2]
CLKin1_DIV 2 Divide by 2 Divider value for CLKin1 R0 19:21 [3]
CLKin1_MUX 0 Bypass Enables or bypasses the CLKin1 divider R0 22:23 [2]
CLKout0_TYPE 1 LVDS Individual clock output format. Select from LVDS/LVPECL. R1 4:6 [3]
CLKout1_TYPE 1 LVDS R1 7:9 [3]
CLKout2_TYPE 1 LVDS R1 10:12 [3]
CLKout3_TYPE 1 LVDS R1 13:15 [3]
CLKout4_TYPE 1 LVDS Individual clock output format. Select
from LVDS/LVPECL/LVCMOS.		 R1 16:19 [4]
CLKout5_TYPE 1 LVDS R1 20:23 [4]
CLKout6_TYPE 1 LVDS R1 24:27 [4]
CLKout7_TYPE 1 LVDS R1 28:31 [4]
CLKout8_TYPE 1 LVDS R2 4:7 [4]
CLKout9_TYPE 1 LVDS R2 8:11 [4]
CLKout10_TYPE 1 LVDS R2 12:15 [4]
CLKout11_TYPE 1 LVDS R2 16:19 [4]
CLKout12_TYPE 1 LVDS R2 20:23 [4]
CLKout13_TYPE 1 LVDS R2 24:27 [4]
CLKout12_13_ADLY 0 No delay Analog delay setting for CLKout12 & CLKout13. R3 4:9 [6]
CLKout12_13_HS 0 No Shift Half shift for digital delay. R3 10
SYNC1_QUAL 0 Not Qualified Allows SYNC operations to be qualified by a clock output R3 11:12 [2]
SYNC0_POL_INV 1 Logic Low Sets the polarity of the SYNC pin when input R3 14
SYNC1_POL_INV 1 Logic Low R3 15
NO_SYNC_CLKout0_3 0 Will sync Disable individual clock groups from being synchronized. R3 16
NO_SYNC_CLKout4_7 0 Will sync R3 17
NO_SYNC_CLKout8_11 0 Will sync R3 18
NO_SYNC_CLKout12_13 0 Will sync R3 19
CLKout0_3_OFFSET_PD 1 Disabled Enables a fixed 5-cycle digital delay offset. R3 20
CLKout4_7_OFFSET_PD 1 Disabled R3 21
CLKout8_11_OFFSET_PD 0 5 clock cycles R3 22
SYNC0_FAST 0 Disabled Enables synchronization circuitry. R3 23
SYNC1_FAST 0 Disabled R3 24
SYNC0_AUTO 1 Automatic SYNC is started by programming a Register R5 R3 25
SYNC1_AUTO 1 Automatic SYNC is started by programming a Register R4 or R5 R3 26
CLKout12_13_DDLY 5 5 clock cycles Digital Delay setting for CLKout12 & CLKout13. R4 4:13 [10]
CLKout0_3_DIV 1 Divide-by-1 Divider for clock outputs. R5 4:6 [3]
CLKout4_7_DIV 1 Divide-by-1 R5 7:9 [3]
CLKout8_11_DIV 1 Divide-by-1 R5 10:12 [3]
CLKout12_ADLY_SEL 0 No Delay Enable Digital Delay for CLKout12 R5 13
CLKout13_ADLY_SEL 0 No Delay Enable Digital Delay for CLKout13 R5 14
CLKout12_13_DIV 1 Divide-by-1 Divider for clock output. R5 17:27 [11]
uWireLock 0 Writeable The values of registers R0 to R5 are lockable R15 4