The LMK03328 implements an input crystal oscillator circuitry, known as the Pierce oscillator, shown in Figure 8-16. The oscillator is enabled when R50.7, R50.6, and R29.1 are set to 1, 0, and 1, respectively. The crystal oscillator circuitry includes programmable on-chip capacitances on each leg of the crystal and a damping resistor intended to minimize the overdriven condition of the crystal. The recommended oscillation mode of operation for the input crystal is the fundamental mode and the recommended type of circuit for the crystal is a parallel resonance with low or high pullability. When the secondary reference is set to crystal input, a crystal must be populated and connected to the SECREF_P and SECREF_N pins.

The load capacitance for a crystal refers to all capacitances in the oscillator feedback loop. The capacitances are equal to the amount of capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the correct load capacitance is necessary to provide the oscillation of the crystal within the expected parameters. The LMK03328 has been characterized with 9-pF parallel resonant crystals with a maximum motional resistance of 30 Ω and maximum drive level of 300 µW.

The normalized frequency error of the crystal, due to load capacitance mismatch, can be calculated as Equation 4:

Equation 4.

where

• C_S is the motional capacitance of the crystal
• C₀ is the shunt capacitance of the crystal
• C_L,R is the rated load capacitance for the crystal
• C_L,A is the actual load capacitance in the implemented PCB for the crystal
• Δƒ is the frequency error of the crystal
• ƒ is the rated frequency of the crystal.

The first 3 parameters can be obtained from the crystal vendor.

Figure 8-16 Crystal Input Interface on Secondary Reference

If reducing frequency error of the crystal is critical, a crystal with low pullability must be used. If frequency margining or frequency spiking is desired, a crystal with high pullability must be used to verify that the desired frequency offset is added to the nominal oscillation frequency. A total of ±50-ppm pulling range is obtained with a crystal whose ratio of shunt capacitance to motional capacitance (C₀/C₁) is no more than 250.

The programmable capacitors on LMK03328 can be tuned from 14 pF to 24 pF in steps of 14 fF using either an analog voltage on GPIO5 in soft pin mode or through the I²C in soft pin or hard pin mode. When using crystals with low pullability, the preferred method is to program R86.3 = 1, R86.2 = 0, and program the appropriate binary code to R104 and R105, in this exact order, that sets the required on-chip load capacitance for least frequency error. GPIO4 pin must be tied to VDD and GPIO5 pin must be floating when device is operating in soft pin mode. Table 8-3 shows the binary code for on-chip load capacitance on each leg of crystal.

When using crystals with high pullability, the same method as above can be repeated to set a fixed frequency offset to the nominal oscillation frequency according to Equation 4. In case there is a closed-loop system where the crystal frequency can be dynamically changed based on a control signal, the LMK03328 must operate in soft pin mode, the R86.3 must be programmed to 0, and the R86.2 must be programmed to 1. The GPIO5 pin is now configured as an 8-level input with a full scale range of 0 V to 1.8 V, and every 200 mV corresponds to a frequency change according to Equation 4. There are three possibilities to enable margining feature with the GPIO5:

• Programming R86.3 = 0 and R86.2 = 1. In this case, the status of the GPIO4 pin is ignored.
• When R86.3 = 0 and R86.2 = 0 is programmed, the GPIO4 must be tied to GND. Tying the GPIO4 to VDD disables the GPIO5 for margining purposes, and the R94 and R95 can determine the on-chip load capacitance for the crystal. If any frequency offset is desired at the output, the appropriate binary code must be programmed to R94 and R95.
• When R86.3 = 1 and R86.2 = 0 is programmed, the GPIO4 must be tied to GND. Tying the GPIO4 to VDD disables the GPIO5 for margining purposes and R104 and R105 determine the on-chip load capacitance for the crystal. If any frequency offset is desired at the output, the appropriate binary code must be programmed to R104 and R105.

There are two possibilities to drive the GPIO5 pin:

• The first method is to achieve the desired voltage between 0 V to 1.8 V according to Analog Input Characteristics (GPIO[5]). The pulldown resistor value sets the voltage on the GPIO[5] pin that falls within one of eight settings whose pre-programmed on-chip crystal load capacitances are set by R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, and R103.
• The second method is using a low-pass filtered PWM signal to drive the 8-level GPIO5 pin as shown in Figure 8-17. The PWM signal can be generated from the frequency difference between a highly stable TCXO and the output of LMK03328 that is provided as a feedback into the GPIO5 pin and used to adjust the on-chip load capacitance on the crystal input to reduce frequency errors from the crystal. This is a quick alternative that produces a frequency error at the output of the LMK03328 and can be acceptable to any application when compared to a full-characterization with a chosen crystal to understand the exact load pulling required to minimize frequency error at the output of the LMK03328. More details on frequency margining are provided in Application and Implementation.

Figure 8-17 Crystal Load Capacitance Compensation Using PWM Signal

The incremental load capacitance for each step must be programmed to R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, and R103 according to the trim sensitivity specifications of the chosen crystal. The least significant bit programmed to any of the XO offset register corresponds to a load capacitance delta of about 0.02 pF on the crystal input pins.

Good layout practices are fundamental to the correct operation and reliability of the oscillator. Locating the crystal components close to the SECREF_P and SECREF_N pins is critical to minimize routing distances. Long traces in the oscillator circuit are a very common source of problems. Do not route other signals across the oscillator circuit, and verify that the power and high-frequency traces are routed as far away as possible to avoid crosstalk and noise coupling. If drive level of the crystal must be reduced, a damping resistor (less than 500 Ω) must be accommodated in the layout between the crystal leg and SECREF_P pin. Vias in the oscillator circuit are recommended primarily for connections to the ground plane. Do not share ground connections, but instead make a separate connection to ground for each component that requires grounding. If possible, place multiple vias in parallel with each connection to the ground plane. The layout must be designed to minimize stray capacitance across the crystal to less than 2 pF total under all circumstances to provide proper crystal oscillation.