SNAS668E August 2015 – September 2024 LMK03328
PRODUCTION DATA
Each PLL loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle slip. The PLL unlock is detected when a certain number of cycle slips have been exceeded, at which point the counter is reset. If the loss of lock is intended to toggle a system reset, an RC filter on the status output, which is programmed to indicate loss of lock, is recommended to avoid rare cycle slips from triggering an entire system reset.
| NUMBER | SIGNAL |
|---|---|
| 0 | PRIREF Loss of Signal (LOS) |
| 1 | SECREF Loss of Signal (LOS) |
| 2 | PLL1 Loss of Lock (LOL) |
| 3 | PLL1 R Divider, divided by 2 (when R Divider is not bypassed) |
| 4 | PLL1 N Divider, divided by 2 |
| 5 | PLL2 Loss of Lock (LOL) |
| 6 | PLL2 R Divider, divided by 2 (when R Divider is not bypassed) |
| 7 | PLL2 N Divider, divided by 2 |
| 8 | PLL1 VCO Calibration Active (CAL) |
| 9 | PLL2 VCO Calibration Active (CAL) |
| 10 | Interrupt (INTR) |
| 11 | PLL1 M Divider, divided by 2 (when M Divider is not bypassed) |
| 12 | PLL2 M Divider, divided by 2 (when M Divider is not bypassed) |
| 13 | EEPROM Active |
| 14 | PLL1 Secondary to Primary Switch in Automatic Mode |
| 15 | PLL2 Secondary to Primary Switch in Automatic Mode |
When the status pins are programmed as 3.3-V LVCMOS PLL clock outputs with fast output rise or fall time setting, the pins support up to 200-MHz operation and each output can independently be programmed to different frequencies. Each output has the option to be muted or not, in case the PLL that has that output loses lock, by programming R23 and when muted, the output is held at a static state depending on the programmed output type or polarity in a loss of lock event. To reduce coupling onto the high-speed outputs, the output rise or fall time can be modified in R49 to support slower slew rates.
When either status pin is set as a 3.3-V LVCMOS output, there is significant mixing of these output frequencies into the high speed outputs, especially outputs 4, 5, 6, and 7. If 3.3-V LVCMOS outputs are desired, take proper care during frequency planning with the LMK03328 to verify that the outputs, required with low jitter, are selected from either output 0, 1, 2, or 3. For best jitter performance, using both status pin is recommended to generate complementary 3.3-V LVCMOS outputs at any time.