SNAS668E August 2015 – September 2024 LMK03328
PRODUCTION DATA
The LMK03328 generates eight outputs with less than 0.2-ps rms maximum random jitter in integer PLL mode and less than 0.35-ps rms maximum random jitter in fractional PLL mode through either a crystal input or a clean external reference input.
For each PLL, a differential/single-ended clock or crystal input can be selected as the PLL reference clock. The selected PLL reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input frequency. The VCO frequency for the respective PLLs can be tuned between 4.8 GHz and 5.4 GHz. Both PLL/VCOs are equivalent in performance and functionality. Each PLL offers the flexibility to select a predefined or user-defined loop bandwidth, depending on the needs of the application. Each PLL has a post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7, or 8.
All the output channels can select the divided-down VCO clock from PLL1 or PLL2 as the source for the output divider to set the final output frequency. Some output channels can also independently select the reference input for PLL1 or PLL2 as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase synchronization capability.
All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS or LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL outputs or 2x 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained through the STATUS pins. This is an optional feature in case 3.3-V LVCMOS outputs are required and device status signals are not.
The device allows a self start-up from the on-chip programmable EEPROM or pre-defined ROM memory, which offers multiple custom device modes engineers can select through the pin control to eliminate the need for serial programming. The device registers and on-chip EEPROM settings are fully programmable through a I2C-compatible serial interface. The device target address is programmable in both EEPROM and LSBs, and can be set with a 3-state pin.
The device provides two frequency margining options with glitch-free operation to support system design verification tests (DVT), such as standard compliance and system timing margin testing. A low-cost pullable crystal on the internal crystal oscillator (XO) can support fine frequency margining (in pmm) if the engineer selects this input as the reference to the PLL synthesizer. The frequency margining range is determined by the trim sensitivity of the crystal and the on-chip varactor range. XO frequency margining can be controlled through a pin or I2C control for ease-of-use and high flexibility. Coarse frequency margining (in %) is available on any output channel by changing the output divide value through the I2C interface, which synchronously stops and restarts the output clock to prevent a glitch or runt pulse when the divider is changed.
Internal power conditioning provides excellent power-supply noise rejection (PSNR), which can reduce the cost and complexity of the power delivery network. The analog and digital core blocks operate from a 3.3-V ± 5% supply, and the output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ± 5% supply.