SNAS668E August   2015  – September 2024 LMK03328

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics - Power Supply
    7. 6.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 6.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 6.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 6.10 VCO Characteristics
    11. 6.11 PLL Characteristics
    12. 6.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 6.13 LVCMOS Output Characteristics (STATUS[1:0]
    14. 6.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 6.15 AC-LVPECL Output Characteristics
    16. 6.16 AC-LVDS Output Characteristics
    17. 6.17 AC-CML Output Characteristics
    18. 6.18 HCSL Output Characteristics
    19. 6.19 Power-On/Reset Characteristics
    20. 6.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 6.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 6.22 Analog Input Characteristics (GPIO[5])
    23. 6.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 6.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics
    25. 6.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics
    26. 6.26 Closed-Loop Output Jitter Characteristics
    27. 6.27 PCIe Clock Output Jitter
    28. 6.28 Typical Power Supply Noise Rejection Characteristics
    29. 6.29 Typical Power Supply Noise Rejection Characteristics
    30. 6.30 Typical Closed-Loop Output Spur Characteristics
    31. 6.31 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Block-Level Description
      2. 8.3.2 Device Configuration Control
        1. 8.3.2.1 Hard Pin Mode (HW_SW_CTRL = 1)
          1. 8.3.2.1.1 PLL Blocks
          2. 8.3.2.1.2 Output Buffer Auto Mute
          3. 8.3.2.1.3 Input Block
          4. 8.3.2.1.4 Channel Mux
          5. 8.3.2.1.5 Output Divider
          6. 8.3.2.1.6 Output Driver Format
          7. 8.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 8.3.2.2 Soft Pin Programming Mode (HW_SW_CTRL = 0)
          1. 8.3.2.2.1 Device Config Space
          2. 8.3.2.2.2 PLL Blocks
          3. 8.3.2.2.3 Output Buffer Auto Mute
          4. 8.3.2.2.4 Input Block
          5. 8.3.2.2.5 Channel Mux
          6. 8.3.2.2.6 Output Divider
          7. 8.3.2.2.7 Output Driver Format
          8. 8.3.2.2.8 Status MUX, Divider, and Slew Rate
        3. 8.3.2.3 Register File Reference Convention
    4. 8.4 Device Functional Modes
      1. 8.4.1  Smart Input MUX
      2. 8.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 8.4.3  Crystal Input Interface (SEC_REF)
      4. 8.4.4  Reference Doubler
      5. 8.4.5  Reference (R) Divider
      6. 8.4.6  Input (M) Divider
      7. 8.4.7  Feedback (N) Divider
      8. 8.4.8  Phase Frequency Detector (PFD)
      9. 8.4.9  Charge Pump
      10. 8.4.10 Loop Filter
      11. 8.4.11 VCO Calibration
      12. 8.4.12 Fractional Circuitry
        1. 8.4.12.1 Programmable Dithering Levels
        2. 8.4.12.2 Programmable Delta Sigma Modulator Order
      13. 8.4.13 Post Divider
      14. 8.4.14 High-Speed Output MUX
      15. 8.4.15 High-Speed Output Divider
      16. 8.4.16 High-Speed Clock Outputs
      17. 8.4.17 Output Synchronization
      18. 8.4.18 Status Outputs
        1. 8.4.18.1 Loss of Reference
        2. 8.4.18.2 Loss of Lock (LOL)
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
      8. 8.5.8 Read ROM
      9. 8.5.9 Default Device Configurations in EEPROM and ROM
  10. 9 Register Maps
    1. 9.1 LMK03328 Registers
      1. 9.1.1   VNDRID_BY1 Register; R0
      2. 9.1.2   VNDRID_BY0 Register; R1
      3. 9.1.3   PRODID Register; R2
      4. 9.1.4   REVID Register; R3
      5. 9.1.5   PARTID Register; R4
      6. 9.1.6   PINMODE_SW Register; R8
      7. 9.1.7   PINMODE_HW Register; R9
      8. 9.1.8   TARGETADR Register; R10
      9. 9.1.9   EEREV Register; R11
      10. 9.1.10  DEV_CTL Register; R12
      11. 9.1.11  INT_LIVE Register; R13
      12. 9.1.12  INT_MASK Register; R14
      13. 9.1.13  INT_FLAG_POL Register; R15
      14. 9.1.14  INT_FLAG Register; R16
      15. 9.1.15  INTCTL Register; R17
      16. 9.1.16  OSCCTL2 Register; R18
      17. 9.1.17  STATCTL Register; R19
      18. 9.1.18  MUTELVL1 Register; R20
      19. 9.1.19  MUTELVL2 Register; R21
      20. 9.1.20  OUT_MUTE Register; R22
      21. 9.1.21  STATUS_MUTE Register; R23
      22. 9.1.22  DYN_DLY Register; R24
      23. 9.1.23  REFDETCTL Register; R25
      24. 9.1.24  STAT0_INT Register; R27
      25. 9.1.25  STAT1 Register; R28
      26. 9.1.26  OSCCTL1 Register; R29
      27. 9.1.27  PWDN Register; R30
      28. 9.1.28  OUTCTL_0 Register; R31
      29. 9.1.29  OUTCTL_1 Register; R32
      30. 9.1.30  OUTDIV_0_1 Register; R33
      31. 9.1.31  OUTCTL_2 Register; R34
      32. 9.1.32  OUTCTL_3 Register; R35
      33. 9.1.33  OUTDIV_2_3 Register; R36
      34. 9.1.34  OUTCTL_4 Register; R37
      35. 9.1.35  OUTDIV_4 Register; R38
      36. 9.1.36  OUTCTL_5 Register; R39
      37. 9.1.37  OUTDIV_5 Register; R40
      38. 9.1.38  OUTCTL_6 Register; R41
      39. 9.1.39  OUTDIV_6 Register; R42
      40. 9.1.40  OUTCTL_7 Register; R43
      41. 9.1.41  OUTDIV_7 Register; R44
      42. 9.1.42  CMOSDIVCTRL Register; R45
      43. 9.1.43  CMOSDIV0 Register; R46
      44. 9.1.44  CMOSDIV1 Register; R47
      45. 9.1.45  STATUS_SLEW Register; R49
      46. 9.1.46  IPCLKSEL Register; R50
      47. 9.1.47  IPCLKCTL Register; R51
      48. 9.1.48  PLL1_RDIV Register; R52
      49. 9.1.49  PLL1_MDIV Register; R53
      50. 9.1.50  PLL2_RDIV Register; R54
      51. 9.1.51  PLL2_MDIV Register; R55
      52. 9.1.52  PLL1_CTRL0 Register; R56
      53. 9.1.53  PLL1_CTRL1 Register; R57
      54. 9.1.54  PLL1_NDIV_BY1 Register; R58
      55. 9.1.55  PLL1_NDIV_BY0 Register; R59
      56. 9.1.56  PLL1_FRACNUM_BY2 Register; R60
      57. 9.1.57  PLL1_FRACNUM_BY1 Register; R61
      58. 9.1.58  PLL1_FRACNUM_BY0 Register; R62
      59. 9.1.59  PLL_FRACDEN_BY2 Register; R63
      60. 9.1.60  PLL1_FRACDEN_BY1 Register; R64
      61. 9.1.61  PLL1_FRACDEN_BY0 Register; R65
      62. 9.1.62  PLL1_MASHCTRL Register; R66
      63. 9.1.63  PLL1_LF_R2 Register; R67
      64. 9.1.64  PLL1_LF_C1 Register; R68
      65. 9.1.65  PLL1_LF_R3 Register; R69
      66. 9.1.66  PLL1_LF_C3 Register; R70
      67. 9.1.67  PLL2_CTRL0 Register; R71
      68. 9.1.68  PLL2_CTRL1 Register; R72
      69. 9.1.69  PLL2_NDIV_BY1 Register; R73
      70. 9.1.70  PLL2_NDIV_BY0 Register; R74
      71. 9.1.71  PLL2_FRACNUM_BY2 Register; R75
      72. 9.1.72  PLL2_FRACNUM_BY1 Register; R76
      73. 9.1.73  PLL2_FRACNUM_BY0 Register; R77
      74. 9.1.74  PLL2_FRACDEN_BY2 Register; R78
      75. 9.1.75  PLL2_FRACDEN_BY1 Register; R79
      76. 9.1.76  PLL2_FRACDEN_BY0 Register; R80
      77. 9.1.77  PLL2_MASHCTRL Register; R81
      78. 9.1.78  PLL2_LF_R2 Register; R82
      79. 9.1.79  PLL2_LF_C1 Register; R83
      80. 9.1.80  PLL2_LF_R3 Register; R84
      81. 9.1.81  PLL2_LF_C3 Register; R85
      82. 9.1.82  XO_MARGINING Register; R86
      83. 9.1.83  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      84. 9.1.84  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      85. 9.1.85  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      86. 9.1.86  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      87. 9.1.87  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      88. 9.1.88  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      89. 9.1.89  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      90. 9.1.90  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      91. 9.1.91  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      92. 9.1.92  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      93. 9.1.93  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      94. 9.1.94  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      95. 9.1.95  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      96. 9.1.96  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      97. 9.1.97  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      98. 9.1.98  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      99. 9.1.99  XO_OFFSET_SW_BY1 Register; R104
      100. 9.1.100 XO_OFFSET_SW_BY0 Register; R105
      101. 9.1.101 PLL1_CTRL2 Register; R117
      102. 9.1.102 PLL1_CTRL3 Register; R118
      103. 9.1.103 PLL1_CALCTRL0 Register; R119
      104. 9.1.104 PLL1_CALCTRL1 Register; R120
      105. 9.1.105 PLL2_CTRL2 Register; R131
      106. 9.1.106 PLL2_CTRL3 Register; R132
      107. 9.1.107 PLL2_CALCTRL0 Register; R133
      108. 9.1.108 PLL2_CALCTRL1 Register; R134
      109. 9.1.109 NVMSCRC Register; R135
      110. 9.1.110 NVMCNT Register; R136
      111. 9.1.111 NVMCTL Register; R137
      112. 9.1.112 NVMLCRC Register; R138
      113. 9.1.113 MEMADR_BY1 Register; R139
      114. 9.1.114 MEMADR_BY0 Register; R140
      115. 9.1.115 NVMDAT Register; R141
      116. 9.1.116 RAMDAT Register; R142
      117. 9.1.117 ROMDAT Register; R143
      118. 9.1.118 NVMUNLK Register; R144
      119. 9.1.119 REGCOMMIT_PAGE Register; R145
      120. 9.1.120 POR_CTRL Register; R173
      121. 9.1.121 XOCAPCTRL_BY1 Register; R199
      122. 9.1.122 XOCAPCTRL_BY0 Register; R200
    2. 9.2 EEPROM Map
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Jitter Considerations in SERDES Systems
      2. 10.1.2 Frequency Margining
        1. 10.1.2.1 Fine Frequency Margining
        2. 10.1.2.2 Coarse Frequency Margining
    2. 10.2 Typical Applications
      1. 10.2.1 Application Block Diagram Examples
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Device Selection
            1. 10.2.1.2.1.1 Calculation Using LCM
          2. 10.2.1.2.2 Device Configuration
          3. 10.2.1.2.3 PLL Loop Filter Design
            1. 10.2.1.2.3.1 PLL Loop Filter Design
          4. 10.2.1.2.4 PLL and Clock Output Assignment
          5. 10.2.1.2.5 Spur Mitigation Techniques
            1. 10.2.1.2.5.1 Phase Detector Spurs
            2. 10.2.1.2.5.2 Integer Boundary Fractional Spurs
            3. 10.2.1.2.5.3 Primary Fractional Spurs
            4. 10.2.1.2.5.4 Sub-Fractional Spurs
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Device Power-Up Sequence
      2. 10.3.2 Device Power-Up Timing
      3. 10.3.3 Power Down
      4. 10.3.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.3.4.1 Mixing Supplies
        2. 10.3.4.2 Power-On Reset
        3. 10.3.4.3 Powering Up From Single-Supply Rail
        4. 10.3.4.4 Powering Up From Split-Supply Rails
        5. 10.3.4.5 Slow Power-Up Supply Ramp
        6. 10.3.4.6 Non-Monotonic Power-Up Supply Ramp
        7. 10.3.4.7 Slow Reference Input Clock Start-Up
      5. 10.3.5 Power Supply Bypassing
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Assess Thermal Reliability
        2. 10.4.1.2 Support for PCB Temperature up to 105°C
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 LMK03328 Registers

The LMK03328 registers are shown in the table below. The registers occupy a single unified address space and all registers are accessible at any time. A total of 124 registers are present in the LMK03328.

Table 9-1 LMK03328 Registers
Name Addr Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
VNDRID_BY1 0 0x10 VNDRID[15:8]
VNDRID_BY0 1 0x0B VNDRID[7:0]
PRODID 2 0x32 PRODID[7:0]
REVID 3 0x02 REVID[7:0]
PARTID 4 0x01 PRTID[7:0]
PINMODE_SW 8 0x00 HW_SW_CTRL_MODE GPIO32_SW_MODE[2:0] RESERVED
PINMODE_HW 9 0x00 GPIO_HW_MODE[5:0] RESERVED
TARGETADR 10 0x54 TARGETADR_GPIO1_SW[7:1] RESERVED
EEREV 11 0x00 EEREV[7:0]
DEV_CTL 12 0xD9 RESETN_SW SYNCN_SW RESERVED SYNC_AUTO SYNC_MUTE AONAFTER
LOCK		 PLLSTRTMODE AUTOSTRT
INT_LIVE 13 0x00 LOL1 LOS1 CAL1 LOL2 LOS2 CAL2 SECTOPRI1 SECTOPRI2
INT_MASK 14 0x00 LOL1_MASK LOS1_MASK CAL1_MASK LOL2_MASK LOS2_MASK CAL2_MASK SECTOPRI1_
MASK		 SECTOPRI2_
MASK
INT_FLAG_POL 15 0x00 LOL1_POL LOS1_POL CAL1_POL LOL2_POL LOS2_POL CAL2_POL SECTOPRI1_
POL		 SECTOPRI2_
POL
INT_FLAG 16 0x00 LOL1_INTR LOS1_INTR CAL1_INTR LOL2_INTR LOS2_INTR CAL2_INTR SECTOPRI1_
INTR		 SECTOPRI2_
INTR
INTCTL 17 0x00 RESERVED INT_AND_OR INT_EN
OSCCTL2 18 0x00 RISE_VALID_
SEC		 FALL_VALID_
SEC		 RISE_VALID_
PRI		 FALL_VALID_
PRI		 RESERVED
STATCTL 19 0x00 RESERVED STAT1_SHOOT_THRU_LIMIT STAT0_SHOOT_THRU_LIMIT RESERVED STAT1_OPEND STAT0_OPEND
MUTELVL1 20 0x55 CH3_MUTE_LVL[1:0] CH2_MUTE_LVL[1:0] CH1_MUTE_LVL[1:0] CH0_MUTE_LVL[1:0]
MUTELVL2 21 0x55 CH7_MUTE_LVL[1:0] CH6_MUTE_LVL[1:0] CH5_MUTE_LVL[1:0] CH4_MUTE_LVL[1:0]
OUT_MUTE 22 0xFF CH_7_MUTE CH_6_MUTE CH_5_MUTE CH_4_MUTE CH_3_MUTE CH_2_MUTE CH_1_MUTE CH_0_MUTE
STATUS_MUTE 23 0x02 RESERVED STATUS1_
MUTE		 STATUS0_
MUTE
DYN_DLY 24 0x00 RESERVED DIV_7_DYN_
DLY		 DIV_6_DYN_
DLY		 DIV_5_DYN_
DLY		 DIV_4_DYN_
DLY		 DIV_23_DYN_
DLY		 DIV_01_DYN_
DLY
REFDETCTL 25 0x55 DETECT_MODE_SEC[1:0] DETECT_MODE_PRI[1:0] LVL_SEL_SEC[1:0] LVL_SEL_PRI[1:0]
STAT0_INT 27 0x58 STAT0_SEL[3:0] STAT0_POL RESERVED
STAT1 28 0x28 STAT1_SEL[3:0] STAT1_POL RESERVED
OSCCTL1 29 0x06 DETECT_BYP RESERVED TERM2GND_
SEC		 TERM2GND_
PRI		 DIFFTERM_SEC DIFFTERM_PRI AC_MODE_SEC AC_MODE_PRI
PWDN 30 0x00 RESERVED CMOSCHPWDN CH7PWDN CH6PWDN CH5PWDN CH4PWDN CH23PWDN CH01PWDN
OUTCTL_0 31 0xB0 CH_0_1_MUX OUT_0_SEL[1:0] OUT_0_MODE1[1:0] OUT_0_MODE2[1:0] RESERVED
OUTCTL_1 32 0x30 RESERVED OUT_1_SEL[1:0] OUT_1_MODE1[1:0] OUT_1_MODE2[1:0] RESERVED
OUTDIV_0_1 33 0x01 OUT_0_1_DIV[7:0]
OUTCTL_2 34 0xB0 CH_2_3_MUX OUT_2_SEL[1:0] OUT_2_MODE1[1:0] OUT_2_MODE2[1:0] RESERVED
OUTCTL_3 35 0x30 RESERVED OUT_3_SEL[1:0] OUT_3_MODE1[1:0] OUT_3_MODE2[1:0] RESERVED
OUTDIV_2_3 36 0x03 OUT_2_3_DIV[7:0]
OUTCTL_4 37 0x18 CH_4_MUX[1:0] OUT_4_SEL[1:0] OUT_4_MODE1[1:0] OUT_4_MODE2[1:0]
OUTDIV_4 38 0x02 OUT_4_DIV[7:0]
OUTCTL_5 39 0x18 CH_5_MUX[1:0] OUT_5_SEL[1:0] OUT_5_MODE1[1:0] OUT_5_MODE2[1:0]
OUTDIV_5 40 0x02 OUT_5_DIV[7:0]
OUTCTL_6 41 0x18 CH_6_MUX[1:0] OUT_6_SEL[1:0] OUT_6_MODE1[1:0] OUT_6_MODE2[1:0]
OUTDIV_6 42 0x05 OUT_6_DIV[7:0]
OUTCTL_7 43 0x18 CH_7_MUX[1:0] OUT_7_SEL[1:0] OUT_7_MODE1[1:0] OUT_7_MODE2[1:0]
OUTDIV_7 44 0x05 OUT_7_DIV[7:0]
CMOSDIVCTRL 45 0x0A PLL2CMOSPREDIV[1:0] PLL1CMOSPREDIV[1:0] STATUS1MUX[1:0] STATUS0MUX[1:0]
CMOSDIV0 46 0x00 CMOSDIV0[7:0]
CMOSDIV1 47 0x00 CMOSDIV1[7:0]
STATUS_SLEW 49 0x00 RESERVED STATUS1SLEW[1:0] STATUS0SLEW[1:0]
IPCLKSEL 50 0x95 SECBUFSEL[1:0] PRIBUFSEL[1:0] INSEL_PLL2[1:0] INSEL_PLL1[1:0]
IPCLKCTL 51 0x03 CLKMUX_
BYPASS		 RESERVED SECONSWITCH SECBUFGAIN PRIBUFGAIN
PLL1_RDIV 52 0x00 RESERVED PLL1RDIV[2:0]
PLL1_MDIV 53 0x00 RESERVED PLL1MDIV[4:0]
PLL2_RDIV 54 0x00 RESERVED PLL2RDIV[2:0]
PLL2_MDIV 55 0x00 RESERVED PLL2MDIV[4:0]
PLL1_CTRL0 56 0x1E RESERVED PLL1_P[2:0] PLL1_SYNC_EN PLL1_PDN
PLL1_CTRL1 57 0x18 RESERVED PRI_D PLL1_CP[3:0]
PLL1_NDIV_BY1 58 0x00 RESERVED PLL1_NDIV[11:8]
PLL1_NDIV_BY0 59 0x66 PLL1_NDIV[7:0]
PLL1_
FRACNUM_BY2		 60 0x00 RESERVED PLL1_NUM[21:16]
PLL1_
FRACNUM_BY1		 61 0x00 PLL1_NUM[15:8]
PLL1_
FRACNUM_BY0		 62 0x00 PLL1_NUM[7:0]
PLL1_
FRACDEN_BY2		 63 0x00 RESERVED PLL1_DEN[21:16]
PLL1_
FRACDEN_BY1		 64 0x00 PLL1_DEN[15:8]
PLL1_
FRACDEN_BY0		 65 0x00 PLL1_DEN[7:0]
PLL1_
MASHCTRL		 66 0x0C RESERVED PLL1_DTHRMODE[1:0] PLL1_ORDER[1:0]
PLL1_LF_R2 67 0x24 RESERVED PLL1_LF_R2[5:0]
PLL1_LF_C1 68 0x00 RESERVED PLL1_LF_C1[2:0]
PLL1_LF_R3 69 0x00 RESERVED PLL1_LF_R3[5:0] PLL1_LF_INT_FRAC
PLL1_LF_C3 70 0x00 RESERVED PLL1_LF_C3[2:0]
PLL2_CTRL0 71 0x1E RESERVED PLL2_P[2:0] PLL2_SYNC_EN PLL2_PDN
PLL2_CTRL1 72 0x18 RESERVED SEC_D PLL2_CP[3:0]
PLL2_NDIV_BY1 73 0x00 RESERVED PLL2_NDIV[11:8]
PLL2_NDIV_BY0 74 0x64 PLL2_NDIV[7:0]
PLL2_
FRACNUM_BY2		 75 0x00 RESERVED PLL2_NUM[21:16]
PLL2_
FRACNUM_BY1		 76 0x00 PLL2_NUM[15:8]
PLL2_
FRACNUM_BY0		 77 0x00 PLL2_NUM[7:0]
PLL2_
FRACDEN_BY2		 78 0x00 RESERVED PLL2_DEN[21:16]
PLL2_
FRACDEN_BY1		 79 0x00 PLL2_DEN[15:8]
PLL2_
FRACDEN_BY0		 80 0x00 PLL2_DEN[7:0]
PLL2_
MASHCTRL		 81 0x0C RESERVED PLL2_DTHRMODE[1:0] PLL2_ORDER[1:0]
PLL2_LF_R2 82 0x24 RESERVED PLL2_LF_R2[5:0]
PLL2_LF_C1 83 0x00 RESERVED PLL2_LF_C1[2:0]
PLL2_LF_R3 84 0x00 RESERVED PLL2_LF_R3[5:0] PLL2_LF_INT_FRAC
PLL2_LF_C3 85 0x00 RESERVED PLL2_LF_C3[2:0]
XO_MARGINING 86 0x00 RESERVED MARGIN_DIG_STEP[2:0] MARGIN_OPTION[1:0] RESERVED RESERVED
XO_OFFSET_
GPIO5_STEP_1_BY1		 88 0x00 RESERVED XOOFFSET_STEP1[9:8]
XO_OFFSET_
GPIO5_STEP_1_BY0		 89 0xDE XOOFFSET_STEP1[7:0]
XO_OFFSET_
GPIO5_STEP_2_BY1		 90 0x01 RESERVED XOOFFSET_STEP2[9:8]
XO_OFFSET_
GPIO5_STEP_2_BY0		 91 0x18 XOOFFSET_STEP2[7:0]
XO_OFFSET_
GPIO5_STEP_3_BY1		 92 0x01 RESERVED XOOFFSET_STEP3[9:8]
XO_OFFSET_
GPIO5_STEP_3_BY0		 93 0x4B XOOFFSET_STEP3[7:0]
XO_OFFSET_
GPIO5_STEP_4_BY1		 94 0x01 RESERVED XOOFFSET_STEP4[9:8]
XO_OFFSET_
GPIO5_STEP_4_BY0		 95 0x86 XOOFFSET_STEP4[7:0]
XO_OFFSET_
GPIO5_STEP_5_BY1		 96 0x01 RESERVED XOOFFSET_STEP5[9:8]
XO_OFFSET_
GPIO5_STEP_5_BY0		 97 0xBE XOOFFSET_STEP5[7:0]
XO_OFFSET_
GPIO5_STEP_6_BY1		 98 0x01 RESERVED XOOFFSET_STEP6[9:8]
XO_OFFSET_
GPIO5_STEP_6_BY0		 99 0xFE XOOFFSET_STEP6[7:0]
XO_OFFSET_
GPIO5_STEP_7_BY1		 100 0x02 RESERVED XOOFFSET_STEP7[9:8]
XO_OFFSET_
GPIO5_STEP_7_BY0		 101 0x47 XOOFFSET_STEP7[7:0]
XO_OFFSET_
GPIO5_STEP_8_BY1		 102 0x02 RESERVED XOOFFSET_STEP8[9:8]
XO_OFFSET_
GPIO5_STEP_8_BY0		 103 0x9E XOOFFSET_STEP8[7:0]
XO_OFFSET_
SW_BY1		 104 0x00 RESERVED XOOFFSET_SW[9:8]
XO_OFFSET_
SW_BY0		 105 0x00 XOOFFSET_SW[7:0]
PLL1_CTRL2 117 0x00 PLL1_STRETCH RESERVED
PLL1_CTRL3 118 0x03 RESERVED PLL1_ENABLE_C3[2:0]
PLL1_
CALCTRL0		 119 0x01 RESERVED PLL1_CLSDWAIT[1:0] PLL1_VCOWAIT[1:0]
PLL1_
CALCTRL1		 120 0x00 RESERVED PLL1_LOOPBW
PLL2_CTRL2 131 0x00 PLL2_STRETCH RESERVED
PLL2_CTRL3 132 0x03 RESERVED PLL2_ENABLE_C3[2:0]
PLL2_
CALCTRL0		 133 0x01 RESERVED PLL2_CLSDWAIT[1:0] PLL2_VCOWAIT[1:0]
PLL2_
CALCTRL1		 134 0x00 RESERVED PLL2_LOOPBW
NVMSCRC 135 0x00 NVMSCRC[7:0]
NVMCNT 136 0x00 NVMCNT[7:0]
NVMCTL 137 0x10 RESERVED REGCOMMIT NVMCRCERR NVMAUTOCRC NVMCOMMIT NVMBUSY RESERVED NVMPROG
NVMLCRC 138 0x00 NVMLCRC[7:0]
MEMADR_BY1 139 0x00 RESERVED MEMADR[11:8]
MEMADR_BY0 140 0x00 MEMADR[7:0]
NVMDAT 141 0x00 NVMDAT[7:0]
RAMDAT 142 0x00 RAMDAT[7:0]
ROMDAT 143 0x00 ROMDAT[7:0]
NVMUNLK 144 0x00 NVMUNLK[7:0]
REGCOMMIT_
PAGE		 145 0x00 RESERVED REGCOMMIT_PG[3:0]
POR_CTRL 173 0x00 RESERVED PLL2_POR_SLOW RESERVED PLL1_POR_SLOW RESERVED
XOCAPCTRL_
BY1		 199 0x00 RESERVED XO_CAP_CTRL[9:8]
XOCAPCTRL_
BY0		 200 0x00 XO_CAP_CTRL[7:0]