SNAS522K September   2011  – December 2023 LMK03806

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Features Description
      1. 7.3.1 Serial MICROWIRE Timing Diagram and Terminology
      2. 7.3.2 Crystal Support With Buffered Outputs
      3. 7.3.3 Integrated Loop Filter Poles
      4. 7.3.4 Integrated VCO
      5. 7.3.5 Clock Distribution
        1. 7.3.5.1 CLKout DIvider
        2. 7.3.5.2 Programmable Output Type
        3. 7.3.5.3 Clock Output Synchronization
      6. 7.3.6 Default Start-Up Clocks
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 General Information
        1. 7.5.1.1 Special Programming Case for R0 to R5 for CLKoutX_Y_DIV > 25
        2. 7.5.1.2 Recommended Initial Programming Sequence
        3. 7.5.1.3 READBACK
          1. 7.5.1.3.1 Readback Example
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Crystal Interface
      2. 8.1.2 Driving OSCin Pins With a Single-Ended Source
      3. 8.1.3 Driving OSCin Pins With a Differential Source
      4. 8.1.4 Frequency Planning With the LMK03806
      5. 8.1.5 Configuring the PLL
        1. 8.1.5.1 Example PLL Configuration
      6. 8.1.6 Digital Lock Detect
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
          1. 8.2.2.1.1 Clock Architect
          2. 8.2.2.1.2 Clock Design Tool
          3. 8.2.2.1.3 Calculation Using LCM
        2. 8.2.2.2 Device Configuration
        3. 8.2.2.3 PLL Loop Filter Design
          1. 8.2.2.3.1 Example Loop Filter Design
        4. 8.2.2.4 Other Device Specific Configuration
          1. 8.2.2.4.1 Digital Lock Detect
        5. 8.2.2.5 Device Programming
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 System Level Diagram
    4. 8.4 Best Design Practices
      1. 8.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 8.4.2 LVPECL Outputs
      3. 8.4.3 Sharing MICROWIRE (SPI) Lines
      4. 8.4.4 SYNC Pin
      5. 8.4.5 CLKout Vcc Pins
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Current Consumption and Power Dissipation Calculations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Register Maps
    1. 10.1  Default Device Register Settings After Power On Reset
    2. 10.2  Register R0 TO R5
      1. 10.2.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
      2. 10.2.2 RESET
      3. 10.2.3 POWERDOWN
      4. 10.2.4 CLKoutX_Y_DIV, Clock Output Divide
    3. 10.3  Registers R6 TO R8
      1. 10.3.1 CLKoutX_TYPE
    4. 10.4  REGISTER R9
    5. 10.5  REGISTER R10
      1. 10.5.1 OSCout1_TYPE, LVPECL Output Amplitude Control
      2. 10.5.2 OSCout0_TYPE
      3. 10.5.3 EN_OSCoutX, OSCout Output Enable
      4. 10.5.4 OSCoutX_MUX, Clock Output Mux
      5. 10.5.5 OSCout_DIV, Oscillator Output Divide
    6. 10.6  REGISTER R11
      1. 10.6.1 NO_SYNC_CLKoutX_Y
      2. 10.6.2 SYNC_POL_INV
      3. 10.6.3 SYNC_TYPE
      4. 10.6.4 EN_PLL_XTAL
    7. 10.7  REGISTER R12
      1. 10.7.1 LD_MUX
      2. 10.7.2 LD_TYPE
      3. 10.7.3 SYNC_PLL_DLD
    8. 10.8  REGISTER R13
      1. 10.8.1 READBACK_TYPE
      2. 10.8.2 GPout0
    9. 10.9  REGISTER 14
      1. 10.9.1 GPout1
    10. 10.10 REGISTER 16
    11. 10.11 REGISTER 24
      1. 10.11.1 PLL_C4_LF, PLL Integrated Loop Filter Component
      2. 10.11.2 PLL_C3_LF, PLL Integrated Loop Filter Component
      3. 10.11.3 PLL_R4_LF, PLL Integrated Loop Filter Component
      4. 10.11.4 PLL_R3_LF, PLL Integrated Loop Filter Component
    12. 10.12 REGISTER 26
      1. 10.12.1 EN_PLL_REF_2X, PLL Reference Frequency Doubler
      2. 10.12.2 PLL_CP_GAIN, PLL Charge Pump Current
      3. 10.12.3 PLL_DLD_CNT
    13. 10.13 REGISTER 28
      1. 10.13.1 PLL_R, PLL R Divider
    14. 10.14 REGISTER 29
      1. 10.14.1 OSCin_FREQ, PLL Oscillator Input Frequency Register
      2. 10.14.2 PLL_N_CAL, PLL N Calibration Divider
    15. 10.15 REGISTER 30
      1. 10.15.1 PLL_P, PLL N Prescaler Divider
      2. 10.15.2 PLL_N, PLL N Divider
    16. 10.16 REGISTER 31
      1. 10.16.1 READBACK_ADDR
      2. 10.16.2 uWire_LOCK
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-27C6394F-1DB7-474C-9A44-329819FB58F8-low.gifFigure 4-1 NKD Package64-Pin WQFNTop View
Table 4-1 Pin Functions
PIN I/O TYPE DESCRIPTION
NAME NO.
CLKout0, CLKout0* 1, 2 O Programmable Clock output 0 (clock group 0).
CLKout1*, CLKout1 3, 4 O Programmable Clock output 1 (clock group 0).
CLKout2, CLKout2* 13, 14 O Programmable Clock output 2 (clock group 1).
CLKout3*, CLKout3 15, 16 O Programmable Clock output 3 (clock group 1).
CLKout4, CLKout4* 19, 20 O Programmable Clock output 4 (clock group 2).
CLKout5*, CLKout5 21, 22 O Programmable Clock output 5 (clock group 2).
CLKout6, CLKout6* 48, 49 O Programmable Clock output 6 (clock group 3).
CLKout7*, CLKout7 50, 51 O Programmable Clock output 7 (clock group 3).
CLKout8, CLKout8* 53, 54 O Programmable Clock output 8 (clock group 4).
CLKout9*, CLKout9 55, 56 O Programmable Clock output 9 (clock group 4).
CLKout10, CLKout10* 58, 59 O Programmable Clock output 10 (clock group 5).
CLKout11*, CLKout11 60, 61 O Programmable Clock output 11 (clock group 5).
CLKuWire 45 I CMOS MICROWIRE Clock Input.
CPout 42 O ANLG Charge pump output.
DAP DAP — GND DIE ATTACH PAD, connect to GND.
DATAuWire 46 I CMOS MICROWIRE Data Input.
Ftest/LD 33 O Programmable Multiplexed Lock Detect and Test output pin.
GND 23 — PWR Ground
GPout0, GPout1 62, 63 O CMOS These pins can be programmed for general purpose output.
LDObyp1 11 — ANLG LDO Bypass, bypassed to ground with 10 µF capacitor.
LDObyp2 12 — ANLG LDO Bypass, bypassed to ground with a 0.1 µF capacitor.
LEuWire 44 I CMOS MICROWIRE Latch Enable Input.
NC 5, 7, 8, 9, 25, 26, 28,29, 34 — Do Not Connect These pins must be left floating. Do NOT ground.
OSCout1, OSCout1* 31, 32 O LVPECL Buffered output 1 of OSCin port.
OSCin, OSCin* 36, 37 I ANLG

Reference input to PLL. Reference input may be:

A Crystal for use with the internal crystal oscillator circuit.

A XO, TCXO, or other external clock. Must be AC Coupled.
OSCout0, OSCout0* 39, 40 O Programmable Buffered output 0 of OSCin port.
Readback 27 O CMOS Pin that can be used to readback register information.
SYNC 6 I CMOS Clock synchronization input.
Vcc1 10 — PWR Power supply for VCO LDO.
Vcc2 17 — PWR Power supply for clock group 1: CLKout2 and CLKout3.
Vcc3 18 — PWR Power supply for clock group 2: CLKout4 and CLKout5.
Vcc4 24 — PWR Power supply for digital.
Vcc5 30 — PWR Power supply for clock inputs.
Vcc6 35 — PWR Power supply. No bypassing required on this pin.
Vcc7 38 — PWR Power supply for OSCin port.
Vcc8 41 — PWR Power supply for PLL charge pump.
Vcc9 43 — PWR Power supply for PLL.
Vcc10 47 — PWR Power supply for clock group 3: CLKout6 and CLKout7.
Vcc11 52 — PWR Power supply for clock group 4: CLKout8 and CLKout9.
Vcc12 57 — PWR Power supply for clock group 5: CLKout10 and CLKout11.
Vcc13 64 — PWR Power supply for clock group 0: CLKout0 and CLKout1.