The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture is capable of 111 fs, RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
PART NUMBER | VCO FREQUENCY | CLOCK INPUTS |
---|---|---|
LMK04208 | 2750 to 3072 MHz | 2 |
DATE | REVISION | NOTES |
---|---|---|
September 2016 | * | Initial release. |
PIN | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1, 2 | NC | – | – | No Connection. These pins must be left floating. |
3, 4 | CLKout0*, CLKout0 | O | Programmable | Clock output 0. |
5 | NC | – | – | No Connection. These pins must be left floating. |
6 | SYNC | I/O | Programmable | CLKout Synchronization input or programmable status pin. |
7, 8, 9 | NC | – | – | No Connection. These pins must be left floating. |
10 | Vcc1 | PWR | Power supply for VCO LDO. | |
11 | LDObyp1 | ANLG | LDO Bypass, bypassed to ground with 10-µF capacitor. | |
12 | LDObyp2 | ANLG | LDO Bypass, bypassed to ground with a 0.1-µF capacitor. | |
13, 14 | CLKout1, CLKout1* | O | Programmable | Clock output 1. |
15, 16 | NC | – | – | No Connection. These pins must be left floating. |
17 | Vcc2 | PWR | Power supply for clock output 1. | |
18 | Vcc3 | PWR | Power supply for clock output 2. | |
19, 20 | NC | – | – | No Connection. These pins must be left floating. |
21, 22 | CLKout2*, CLKout2 | O | Programmable | Clock output 2. |
23 | GND | PWR | Ground. | |
24 | Vcc4 | PWR | Power supply for digital. | |
25, 26 | CLKin1, CLKin1* | I | ANLG | Reference Clock Input Port 1 for PLL1. AC or DC Coupled. |
FBCLKin, FBCLKin* | Feedback input for external clock feedback input (0-delay mode). AC or DC Coupled. | |||
Fin/Fin* | External VCO input (External VCO mode). AC or DC Coupled. | |||
27 | Status_Holdover | I/O | Programmable | Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming. |
28, 29 | CLKin0, CLKin0* | I | ANLG | Reference Clock Input Port 0 for PLL1. AC or DC Coupled. |
30 | Vcc5 | PWR | Power supply for clock inputs. | |
31, 32 | NC | – | – | No Connection. These pins must be left floating. |
33 | Status_LD | I/O | Programmable | Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming. |
34 | CPout1 | O | ANLG | Charge pump 1 output. |
35 | Vcc6 | PWR | Power supply for PLL1, charge pump 1. | |
36, 37 | OSCin, OSCin* | I | ANLG | Feedback to PLL1, Reference input to PLL2. AC Coupled. |
38 | Vcc7 | PWR | Power supply for OSCin, OSCout, and PLL2 circuitry.(2) | |
39, 40 | OSCout, OSCout* | O | Programmable | Buffered output of OSCin port.(2) |
41 | Vcc8 | PWR | Power supply for PLL2, charge pump 2. | |
42 | CPout2 | O | ANLG | Charge pump 2 output. |
43 | Vcc9 | PWR | Power supply for PLL2. | |
44 | LEuWire | I | CMOS | MICROWIRE Latch Enable Input. |
45 | CLKuWire | I | CMOS | MICROWIRE Clock Input. |
46 | DATAuWire | I | CMOS | MICROWIRE Data Input. |
47 | Vcc10 | PWR | Power supply for clock output 3. | |
48, 49 | CLKout3, CLKout3* | O | Programmable | Clock output 3. |
50, 51 | NC | – | – | No Connection. These pins must be left floating. |
52 | Vcc11 | PWR | Power supply for clock output 4. | |
53, 54 | CLKout4, CLKout4* | O | Programmable | Clock output 4. |
55, 56 | NC | – | – | No Connection. These pins must be left floating. |
57 | Vcc12 | PWR | Power supply for clock output 5. | |
58, 59 | CLKout5, CLKout5* | O | Programmable | Clock output 5. |
60, 61 | NC | – | – | No Connection. These pins must be left floating. |
62 | Status_CLKin0 | I/O | Programmable | NC. Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming. |
63 | Status_CLKin1 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming. |
64 | Vcc13 | PWR | Power supply for clock output 0. | |
DAP | DAP | – | GND | DIE ATTACH PAD, connect to GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage (2) | –0.3 | 3.6 | V |
VIN | Input voltage | –0.3 | VCC + 0.3 | V |
TL | Lead temperature (solder 4 seconds) | 260 | °C | |
TJ | Junction temperature | 150 | °C | |
IIN | Differential input current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) |
± 5 | mA | |
MSL | Moisture Sensitivity Level | 3 | ||
Tstg | Storage temperature | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TJ | Junction temperature | 125 | °C | |||
TA | Ambient temperature | VCC = 3.3 V | –40 | 25 | 85 | °C |
VCC | Supply voltage | 3.15 | 3.3 | 3.45 | V |
THERMAL METRIC(1) | LMK04208 | UNIT | |
---|---|---|---|
NKD (WQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance on 4-layer JEDEC PCB(2)(8) | 25.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance(3)(9) | 6.9 | °C/W |
RθJB | Junction-to-board thermal resistance(4) | 4.0 | °C/W |
ψJT | Junction-to-top characterization parameter(5) | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter(6) | 4.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance(7) | 0.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CURRENT CONSUMPTION | ||||||
ICC_PD | Power down supply current | 1 | 3 | mA | ||
ICC_CLKS | Supply current with all clocks (CLKoutX) and OSCout enabled as LVDS.(2) | All clock delays disabled, CLKoutX_DIV = 1045, EN_SYNC=0 PLL1 and PLL2 locked. |
445 | 535 | mA | |
CLKin0/0* and CLKin1/1* INPUT CLOCK SPECIFICATIONS | ||||||
fCLKin | Clock input frequency(3) | 0.001 | 500 | MHz | ||
SLEWCLKin(4) | Clock input slew rate(17) | 20% to 80% | 0.15 | 0.5 | V/ns | |
VIDCLKin | Clock input Differential input voltage (see (1) and Figure 8) |
AC coupled CLKinX_BUF_TYPE = 0 (Bipolar) |
0.25 | 1.55 | |V| | |
VSSCLKin | 0.5 | 3.1 | Vpp | |||
VIDCLKin | AC coupled CLKinX_BUF_TYPE = 1 (MOS) |
0.25 | 1.55 | |V| | ||
VSSCLKin | 0.5 | 3.1 | Vpp | |||
VCLKin | Clock input Single-ended input voltage(17) |
AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 0 (Bipolar) |
0.25 | 2.4 | Vpp | |
AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 1 (MOS) |
0.25 | 2.4 | Vpp | |||
VCLKin0-offset | DC offset voltage between CLKin0/CLKin0* CLKin0* - CLKin0 |
Each pin AC coupled CLKin0_BUF_TYPE = 0 (Bipolar) |
20 | mV | ||
VCLKin1-offset | DC offset voltage between CLKin1/CLKin1* CLKin1* - CLKin1 |
0 | mV | |||
VCLKinX-offset | DC offset voltage between CLKinX/CLKinX* CLKinX* - CLKinX |
Each pin AC coupled CLKinX_BUF_TYPE = 1 (MOS) |
55 | mV | ||
VCLKin- VIH | High input voltage | DC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 1 (MOS) |
2.0 | VCC | V | |
VCLKin- VIL | Low input voltage | 0.0 | 0.4 | V | ||
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | ||||||
fFBCLKin | Clock input frequency(17) | AC coupled (CLKinX_BUF_TYPE = 0) MODE = 2 or 8; FEEDBACK_MUX = 6 |
0.001 | 1000 | MHz | |
fFin | Clock input frequency(17) | AC coupled (CLKinX_BUF_TYPE = 0) MODE = 3 or 11 |
0.001 | 3100 | MHz | |
VFBCLKin/Fin | Single Ended Clock input voltage(17) |
AC coupled; (CLKinX_BUF_TYPE = 0) |
0.25 | 2.0 | Vpp | |
SLEWFBCLKin/Fin | Slew rate on CLKin(17)(4) | AC coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0) |
0.15 | 0.5 | V/ns | |
PLL1 SPECIFICATIONS | ||||||
fPD1 | PLL1 phase detector frequency | 40 | MHz | |||
ICPout1SOURCE | PLL1 charge Pump source current(5) |
VCPout1 = VCC/2, PLL1_CP_GAIN = 0 | 100 | µA | ||
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 | 200 | |||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 | 400 | |||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 3 | 1600 | |||||
ICPout1SINK | PLL1 charge Pump sink current(5) |
VCPout1=VCC/2, PLL1_CP_GAIN = 0 | –100 | µA | ||
VCPout1=VCC/2, PLL1_CP_GAIN = 1 | –200 | |||||
VCPout1=VCC/2, PLL1_CP_GAIN = 2 | –400 | |||||
VCPout1=VCC/2, PLL1_CP_GAIN = 3 | –1600 | |||||
ICPout1%MIS | Charge pump Sink/source mismatch |
VCPout1 = VCC/2, T = 25 °C | 3% | 10% | ||
ICPout1VTUNE | Magnitude of charge pump current variation vs. charge pump voltage | 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C |
4% | |||
ICPout1%TEMP | Charge pump current vs. temperature variation |
4% | ||||
ICPout1 TRI | Charge Pump TRI-STATE leakage current | 0.5 V < VCPout < VCC - 0.5 V | 5 | nA | ||
PN10kHz | PLL 1/f noise at 10 kHz offset.(9) Normalized to 1 GHz Output Frequency | PLL1_CP_GAIN = 400 µA | –117 | dBc/Hz | ||
PLL1_CP_GAIN = 1600 µA | –118 | |||||
PN1Hz | Normalized phase noise contribution(10) | PLL1_CP_GAIN = 400 µA | –221.5 | dBc/Hz | ||
PLL1_CP_GAIN = 1600 µA | –223 | |||||
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | ||||||
fOSCin | PLL2 reference input(6) | 500 | MHz | |||
SLEWOSCin | PLL2 reference clock minimum slew rate on OSCin(17) | 20% to 80% | 0.15 | 0.5 | V/ns | |
VOSCin | Input voltage for OSCin or OSCin*(17) | AC coupled; Single-ended (Unused pin AC coupled to GND) | 0.2 | 2.4 | Vpp | |
VIDOSCin | Differential voltage swing (see Figure 8) | AC coupled | 0.2 | 1.55 | |V| | |
VSSOSCin | 0.4 | 3.1 | Vpp | |||
VOSCin-offset | DC offset voltage between OSCin/OSCin* OSCinX* - OSCinX |
Each pin AC coupled | 20 | mV | ||
fdoubler_max | Doubler input frequency(17) | EN_PLL2_REF_2X = 1;(7)
OSCin Duty Cycle 40% to 60% |
155 | MHz | ||
CRYSTAL OSCILLATOR MODE SPECIFICATIONS | ||||||
fXTAL | Crystal frequency range(17) | RESR < 40 Ω | 6 | 20.5 | MHz | |
PXTAL | Crystal power dissipation(8) | Vectron VXB1 crystal, 20.48 MHz, RESR < 40 Ω XTAL_LVL = 0 |
100 | µW | ||
CIN | Input capacitance of LMK04208 OSCin port |
-40 to +85 °C | 6 | pF | ||
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | ||||||
fPD2 | Phase detector frequency | 155 | MHz | |||
ICPoutSOURCE | PLL2 charge pump source current(5) | VCPout2=VCC/2, PLL2_CP_GAIN = 0 | 100 | µA | ||
VCPout2=VCC/2, PLL2_CP_GAIN = 1 | 400 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 2 | 1600 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 3 | 3200 | |||||
ICPoutSINK | PLL2 charge pump sink current(5) | VCPout2=VCC/2, PLL2_CP_GAIN = 0 | –100 | µA | ||
VCPout2=VCC/2, PLL2_CP_GAIN = 1 | –400 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 2 | –1600 | |||||
VCPout2=VCC/2, PLL2_CP_GAIN = 3 | –3200 | |||||
ICPout2%MIS | Charge pump sink/source mismatch | VCPout2=VCC/2, TA = 25 °C | 3% | 10% | ||
ICPout2VTUNE | Magnitude of charge pump current vs. charge pump voltage variation | 0.5 V < VCPout2 < VCC - 0.5 V TA = 25 °C |
4% | |||
ICPout2%TEMP | Charge pump current vs. Temperature variation |
4% | ||||
ICPout2TRI | Charge pump leakage | 0.5 V < VCPout2 < VCC - 0.5 V | 10 | nA | ||
PN10kHz | PLL 1/f Noise at 10 kHz offset(9)
Normalized to 1 GHz output frequency |
PLL2_CP_GAIN = 400 µA | –118 | dBc/Hz | ||
PLL2_CP_GAIN = 3200 µA | –121 | |||||
PN1Hz | Normalized Phase Noise Contribution(10) | PLL2_CP_GAIN = 400 µA | –222.5 | dBc/Hz | ||
PLL2_CP_GAIN = 3200 µA | –227 | |||||
INTERNAL VCO SPECIFICATIONS | ||||||
fVCO | VCO tuning range | LMK04208 | 2750 | 3072 | MHz | |
KVCO | Fine tuning sensitivity (The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range). |
LMK04208 | 20 to 36 | MHz/V | ||
|ΔTCL| | Allowable Temperature Drift for Continuous Lock(11) (17) | After programming R30 for lock, no changes to output configuration are permitted to ensure continuous lock | 125 | °C | ||
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING a COMMERCIAL QUALITY VCXO(14) | ||||||
L(f)CLKout | LMK04208 fCLKout = 245.76 MHz SSB Phase noise Measured at clock outputs Value is average for all output types(12) |
Offset = 1 kHz | –122.5 | dBc/Hz | ||
Offset = 10 kHz | –132.9 | |||||
Offset = 100 kHz | –135.2 | |||||
Offset = 800 kHz | –143.9 | |||||
Offset = 10 MHz; LVDS | –156.0 | |||||
Offset = 10 MHz; LVPECL 1600 mVpp | –157.5 | |||||
Offset = 10 MHz; LVCMOS | –157.1 | |||||
JCLKout
LVDS/LVPECL/LVCMOS |
LMK04208(12)
fCLKout = 245.76 MHz Integrated RMS jitter |
BW = 12 kHz to 20 MHz | 111 | fs, RMS | ||
BW = 100 Hz to 20 MHz | 123 | |||||
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW NOISE CRYSTAL OSCILLATOR CIRCUIT (15) | ||||||
LMK04208 fCLKout = 245.76 MHz Integrated RMS jitter |
BW = 12 kHz to 20 MHz XTAL_LVL = 3 |
192 | fs rms | |||
BW = 100 Hz to 20 MHz XTAL_LVL = 3 |
450 | |||||
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY | ||||||
fCLKout-startup | Default output clock frequency at device power on(16) | CLKout4, LVDS, LMK04208 | 90 | 110 | 130 | MHz |
CLOCK SKEW and DELAY | ||||||
|TSKEW| | Maximum CLKoutX to CLKoutY(17)(13) | LVDS-to-LVDS, T = 25 °C, FCLK = 800 MHz, RL= 100 Ω AC coupled |
30 | ps | ||
LVPECL-to-LVPECL, T = 25 °C, FCLK = 800 MHz, RL= 100 Ω emitter resistors = 240 Ω to GND AC coupled |
30 | |||||
Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout(17)(13) | RL = 50 Ω, CL = 5 pF, T = 25 °C, FCLK = 100 MHz. |
100 | ||||
MixedTSKEW | LVDS or LVPECL to LVCMOS | Same device, T = 25 °C, 250 MHz |
750 | ps | ||
td0-DELAY | CLKin to CLKoutX delay(13) | MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0 |
1850 | ps | ||
MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0; VCO Frequency = 2949.12 MHz Analog delay select = 0; Feedback clock digital delay = 11; Feedback clock half step = 1; Output clock digital delay = 5; Output clock half step = 0; |
0 | |||||
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1 | ||||||
fCLKout | Maximum frequency(17)(18) | RL = 100 Ω | 1536 | MHz | ||
VOD | Differential output voltage (see Figure 9) | T = 25 °C, DC measurement AC coupled to receiver input R = 100-Ω differential termination |
250 | 400 | 450 | |mV| |
VSS | 500 | 800 | 900 | mVpp | ||
ΔVOD | Change in magnitude of VOD for complementary output states | –50 | 50 | mV | ||
VOS | Output offset voltage | 1.125 | 1.25 | 1.375 | V | |
ΔVOS | Change in VOS for complementary output states | 35 | |mV| | |||
TR / TF | Output rise time | 20% to 80%, RL = 100 Ω | 200 | ps | ||
Output fall time | 80% to 20%, RL = 100 Ω | |||||
ISA
ISB |
Output short circuit current single-ended |
Single-ended output shorted to GND T = 25 °C |
–24 | 24 | mA | |
ISAB | Output short circuit current - differential | Complimentary outputs tied together | –12 | 12 | mA | |
LVPECL CLOCK OUTPUTS (CLKoutX) | ||||||
fCLKout | Maximum frequency(17)(18) | 1536 | MHz | |||
TR / TF | 20% to 80% output rise | RL = 100 Ω, emitter resistors = 240 Ω to GND CLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp) |
150 | ps | ||
80% to 20% output fall time | ||||||
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2 | ||||||
VOH | Output high voltage | T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.4 V |
VCC – 1.03 | V | ||
VOL | Output low voltage | VCC – 1.41 | V | |||
VOD | Output voltage (see Figure 9) | 305 | 380 | 440 | |mV| | |
VSS | 610 | 760 | 880 | mVpp | ||
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3 | ||||||
VOH | Output high voltage | T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.7 V |
VCC – 1.07 | V | ||
VOL | Output low voltage | VCC – 1.69 | V | |||
VOD | Output voltage (see Figure 9) | 545 | 625 | 705 | |mV| | |
VSS | 1090 | 1250 | 1410 | mVpp | ||
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4 | ||||||
VOH | Output high voltage | T = 25 °C, DC Measurement Termination = 50 Ω to VCC - 2.0 V |
VCC – 1.10 | V | ||
VOL | Output low voltage | VCC – 1.97 | V | |||
VOD | Output voltage (see Figure 9) | 660 | 870 | 965 | |mV| | |
VSS | 1320 | 1740 | 1930 | mVpp | ||
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5 | ||||||
VOH | Output high voltage | T = 25 °C, DC Measurement Termination = 50 Ω to VCC - 2.3 V |
VCC – 1.13 | V | ||
VOL | Output low voltage | VCC – 2.20 | V | |||
VOD | Output voltage Figure 9 | 800 | 1070 | 1200 | |mV| | |
VSS | 1600 | 2140 | 2400 | mVpp | ||
LVCMOS CLOCK OUTPUTS (CLKoutX) | ||||||
fCLKout | Maximum frequency(17)(18) | 5 pF Load | 250 | MHz | ||
VOH | Output high voltage | 1 mA Load | VCC – 0.1 | V | ||
VOL | Output low voltage | 1 mA Load | 0.1 | V | ||
IOH | Output high current (source) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | ||
IOL | Output low current (sink) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | ||
DUTYCLK | Output duty cycle(17) | VCC/2 to VCC/2, FCLK = 100 MHz T = 25 °C |
45% | 50% | 55% | |
TR | Output rise time | 20% to 80%, RL = 50 Ω, CL = 5 pF |
400 | ps | ||
TF | Output fall time | 80% to 20%, RL = 50 Ω, CL = 5 pF |
400 | ps | ||
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC) | ||||||
VOH | High-level output voltage | IOH = -500 µA | VCC – 0.4 | V | ||
VOL | Low-level output voltage | IOL = 500 µA | 0.4 | V | ||
DIGITAL INPUTS (Status_CLKinX, SYNC) | ||||||
VIH | High-level input voltage | 1.6 | VCC | V | ||
VIL | Low-level input voltage | 0.4 | V | |||
IIH | High-level input current VIH = VCC |
Status_CLKinX_TYPE = 0 (High Impedance) |
–5 | 5 | µA | |
Status_CLKinX_TYPE = 1 (Pull-up) |
–5 | 5 | ||||
Status_CLKinX_TYPE = 2 (Pull-down) |
10 | 80 | ||||
IIL | Low-level input current VIL = 0 V |
Status_CLKinX_TYPE = 0 (High Impedance) |
–5 | 5 | µA | |
Status_CLKinX_TYPE = 1 (Pull-up) |
–40 | -5 | ||||
Status_CLKinX_TYPE = 2 (Pull-down) |
–5 | 5 | ||||
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire) | ||||||
VIH | High-level input voltage | 1.6 | VCC | V | ||
VIL | Low-level input voltage | 0.4 | V | |||
IIH | High-level input current | VIH = VCC | 5 | 25 | µA | |
IIL | Low-level input current | VIL = 0 | –5 | 5 | µA |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TECS | LE to clock set up time | See Figure 1 through Figure 4 | 25 | ns | ||
TDCS | Data to clock set up time | See Figure 1 | 25 | ns | ||
TCDH | Clock to data hold time | See Figure 1 | 8 | ns | ||
TCWH | Clock pulse width high | See Figure 1, Figure 2, and Figure 4 | 25 | ns | ||
TCWL | Clock pulse width low | See Figure 1, Figure 2, and Figure 4 | 25 | ns | ||
TCES | Clock to LE set up time | See Figure 1 through Figure 4 | 25 | ns | ||
TEWH | LE pulse width | See Figure 1, Figure 2, and Figure 4 | 25 | ns | ||
TCR | Falling clock to readback time | See Figure 4 | 25 | ns |
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.
Figure 8 illustrates the two different definitions side-by-side for inputs and Figure 9 illustrates the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
See AN-912, Common Data Transmission Parameters and their Definitions SNLA036, for more information.
In default mode of operation, dual PLL mode with internal VCO, the Phase Frequency Detector in PLL1 compares the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external VCXO or crystal attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1 should be narrow to provide an ultra clean reference clock from the external VCXO or crystal to the OSCin/OSCin* pins for PLL2.
The Phase Frequency Detector in PLL2 compares the external VCXO or crystal to the internal VCO after the reference and feedback dividers. The VCXO or crystal on the OSCin input is divided by PLL2 R divider. The feedback from the internal VCO is divided by the PLL2 Prescaler, the PLL2 N divider, and optionally the VCO divider.
The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is also placed on the distribution path for the Clock Distribution section. The clock distribution consists of 6 outputs. Each clock output allows the user to select a divide value, a digital delay value, and an analog delay. The 6 clock outputs drive programmable output buffers. Two clock outputs allow their input signal to be from the OSCin port directly.
When a 0-delay mode is used, a clock output will be passed through the feedback mux to the PLL1 N Divider for synchronization and 0-delay.
When an external VCO mode is used, the Fin port will be used to input an external VCO signal. PLL2 Phase comparison will now be with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may not be used. One less clock input is available when using an external VCO mode.
When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.
The dual loop PLL architecture of the LMK04208 provides the lowest jitter performance over the widest range of output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. This cleaned reference clock provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or tunable crystal.
Ultra low jitter is achieved by allowing the external VCXO or crystal’s phase noise to dominate the final output phase noise at low offset frequencies and the internal (or external) VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.
The LMK04208 allows subsets of the device to be used to increase the flexibility of device. These different modes are selected using MODE: Device Mode. For instance:
See Device Functional Modes for more information on these modes.
The LMK04208 has two reference clock inputs for PLL1: CLKin0 and CLKin1. Ref Mux selects CLKin0 or CLKin1. Automatic or manual switching occurs between the inputs.
CLKin0 and CLKin1 each have input dividers. The input divider allows different clock input frequencies to be normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching. By programming these dividers such that the frequency presented to the input of the PLL1 R divider is the same prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another CLKin port with a different frequency.
CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).
Fast manual switching between reference clocks is possible with external pins Status_CLKin0 and Status_CLKin1.
The LMK04208 integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to perform jitter cleaning.
The LMK04208 must be programmed to enable Crystal mode.
The LMK04208 provides a dedicated output, OSCout, which is a buffered copy of the PLL2 reference input (see Functional Block Diagram for a block diagram of this implementation). The PLL2 reference input is typically a low noise VCXO or Crystal. When using a VCXO, this output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04208 is programmed. See Clock Output Synchronization and MODE: Device Mode for further reference of these outputs
The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.
The dedicated output buffer OSCout can output frequency lower than the VCXO or Crystal frequency by programming the OSC Divider. The OSC Divider value range is 2 to 8.
Two clock outputs can also be programmed to be driven by OSCin. This allows a total of 2 additional differential outputs to be buffered outputs of OSCin. When programmed in this way, a total of 3 differential or 6 single-ended outputs can be driven by a buffered copy of OSCin.
VCXO/Crystal buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion of SYNC will still cause these outputs to become low temporarily. Since these outputs will turn off and on asynchronously with respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur on the buffered clock outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX bits are set these outputs will not be affected by the SYNC event except that the phase relationship will change with the other synchronized clocks unless a buffered clock output is used as a qualification clock during SYNC.
The LMK04208 supports holdover operation to keep the clock outputs on frequency with minimum drift when the reference is lost until a valid reference clock signal is re-established.
The LMK04208 features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter response. The integrated programmable resistors and capacitors compliment external components mounted near the chip.
These integrated components can be effectively disabled by programming the integrated resistors and capacitors to their minimum values.
The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or a divided version of the VCO for the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and N-divider.
The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd divide values.
The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.
The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04208. An external VCO may be needed to meet stringent output phase noise/jitter requirements in some applications, such as multi-carrier GSM.
An external VCO is permitted in single PLL, dual PLL, or 0-delay dual PLL mode. In 0-delay dual PLL mode, the clock outputs driven from the external VCO can have deterministic phase with the clock input.
Using an external VCO reduces the number of available clock inputs by one. The VCO divider cannot be used with an external VCO.
The LMK04208 features a total of 6 differential outputs driven from the internal or external VCO.
All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 12 outputs are available.
If the buffered OSCin output OSCout is included in the total number of clock outputs the LMK04208 is able to distribute, then up to 7 differential clocks or up to 14 single-ended clocks may be generated with the LMK04208.
The following sections discuss specific features of the clock distribution channels that allow the user to control various aspects of the output clocks.
Each clock has a single clock output divider. The divider supports a divide range of 1 to 1045 (even and odd) with 50% output duty cycle. When divides of 26 or greater are used, the divider/delay block uses extended mode.
The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in normal mode instead of extended mode. This can result in a small current saving if enabling the VCO Divider allows 3 or more clock output divides to change from extended to normal mode.
See Clock Distribution section for details on both a fine (analog) and coarse (digital) delay for phase adjustment of the clock outputs.
The fine (analog) delay allows a nominal 25-ps step size and range from 0 to 475 ps of total delay. Enabling the analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay, glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the minimum-ensured maximum output frequency of 1536 MHz.
The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the period of the clock distribution path by using the CLKoutX_HS bit provided the output divide value is greater than 1. For example, a 2-GHz VCO frequency without the use of the VCO divider results in 250 ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.
There are 3 different ways to use the digital (coarse) delay:
These are further discussed in Clock Distribution.
For increased flexibility all LMK04208 clock outputs (CLKoutX) and OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type.
Any LVPECL output type can be programmed to 700-, 1200-, 1600-, or 2000-mVpp amplitude levels. The 2000-mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential swing for compatibility with many data converters and is also known as 2VPECL.
Using the SYNC input causes all active clock outputs to share a rising edge. See Clock Output Synchronization (SYNC) for more information.
The SYNC event also causes the digital delay values to take effect.
The 0-delay mode synchronizes the input clock phase to the output clock phase. The 0-delay feedback may be performed with an internal feedback loop from any of the clock groups or with an external feedback loop into the FBCLKin port as selected by the FEEDBACK_MUX.
Without using 0-delay mode, there will be D possible fixed phase relationships from clock input to clock output depending on the clock output divide value.
Using an external 0-delay feedback reduces the number of available clock inputs by one.
Before the LMK04208 is programmed, CLKout4 is enabled and operating at a nominal frequency and CLKout3 and OSCout are enabled and operating at the OSCin frequency. These clocks can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04208 is programmed.
For CLKout3 and OSCout to work before the LMK04208 is programmed, the device must not be using Crystal mode.
The LMK04208 provides status pins which can be monitored for feedback or in some cases used for input depending upon device programming. For example:
The status pins can be programmed to a variety of other outputs including analog lock detect, PLL divider outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to the Programming of this datasheet for more information. Default pin programming is captured in Table 17.
Programmed registers may be read back using the MICROWIRE interface. For readback, one of the status pins must be programmed for readback mode.
At no time may registers be programed to values other than the valid states defined in the datasheet.
The reference clock inputs for PLL1 may be selected from either CLKin0 or CLKin1. The user has the capability to manually select one of the inputs or to configure an automatic switching mode of operation. See Input Clock Switching for more info.
CLKin0 and CLKin1 have dividers which allow the device to switch between reference inputs of different frequencies automatically without needing to reprogram the PLL1 R divider. The CLKin pre-divider values are 1, 2, 4, and 8.
CLKin1 input can alternatively be used for external feedback in 0-delay mode (FBCLKin) or for an external VCO input port (Fin).
The feedback from the external oscillator being locked with PLL1 drives the OSCin/OSCin* pins. Internally this signal is routed to the PLL1 N Divider and to the reference input for PLL2.
This input may be driven with either a single-ended or differential signal and must be AC coupled. If operated in single ended mode, the unused input must be connected to GND with a 0.1-µF capacitor.
The internal circuitry of the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, a varactor diode, and a small number of other external components may be used to implement the oscillator. The internal oscillator circuit is enabled by setting the EN_PLL2_XTAL bit. See EN_PLL2_XTAL.
Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the CLKin_SELECT_MODE register.
Below is information about how the active input clock is selected and what causes a switching event in the various clock input selection modes.
When CLKin_SELECT_MODE is 0 or 1 then CLKin0 or CLKin1 respectively is always selected as the active input clock. Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is disabled with EN_CLKinX = 0.
When CLKin_SELECT_MODE is 3, the pins Status_CLKin0 and Status_CLKin1 select which clock input is active.
STATUS_CLKin1 | STATUS_CLKin0 | ACTIVE CLOCK |
---|---|---|
0 | 0 | CLKin0 |
0 | 1 | CLKin1 |
1 | 0 | Reserved |
1 | 1 | Holdover |
The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX = 1) that could be switched to.
When in the pin select mode, the host can monitor conditions of the clocking system which could cause the host to switch the active clock input. The LMK04208 device can also provide indicators on the Status_LD and Status_HOLDOVER like DAC Rail, PLL1 DLD, PLL1 and PLL2 DLD which the host can use in determining which clock input to use as active clock input.
When an input clock switch event is triggered and holdover mode is disabled, the active clock input immediately switches to the selected clock. When PLL1 is designed with a narrow loop bandwidth, the switching transient is minimized.
When an input clock switch event is triggered and holdover mode is enabled, the device will enter holdover mode and remain in holdover until a holdover exit condition is met as described in Holdover Mode. Then the device will complete the reference switch to the pin selected clock input.
When CLKin_SELECT_MODE is 4, the active clock is selected in priority order of enabled clock inputs starting upon an input clock switch event. The priority order of the clocks is CLKin0 → CLKin1 → CLKin0, and so forth.
For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX.
Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SELECT_MODE to the manual mode which selects the desired clock input (CLKin0 or 1). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SELECT_MODE = 4.
A loss of lock as indicated by PLL1’s DLD signal (PLL1_DLD = 0) will cause an input clock switch event if DISABLE_DLD1_DET = 0. PLL1 DLD must go high (PLL1_DLD = 1) in between input clock switching events.
If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses the DAC high or low threshold, holdover mode will be entered. Since PLL1_DLD = 0 in holdover a clock input switching event will occur.
Clock switch event with holdover enabled is recommended in this input clock switching mode. When an input clock switch event occurs, holdover mode is entered and the active clock is set to the clock input defined by the Status_CLKinX pins. When the new active clock meets the holdover exit conditions, holdover is exited and the active clock will continue to be used as a reference until another input clock switch event. PLL1 DLD must go high in between input clock switching events.
When CLKin_SELECT_MODE is 6, the active clock is selected using the Status_CLKinX pins upon an input clock switch event according to Table 2.
Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SELECT_MODE to the manual mode which selects the desired clock input (CLKin0 or 1). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SELECT_MODE = 6.
An input clock switch event is generated by a loss of lock as indicated by PLL1's DLD signal (PLL1 DLD = 0).
If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses the DAC threshold, holdover mode will be entered. Since PLL1_DLD = 0 in holdover, a clock input switching event will occur.
Clock switch event with holdover enabled is recommended in this input clock switching mode. When an input clock switch event occurs, holdover mode is entered and the active clock is set to the clock input defined by the Status_CLKinX pins. When the new active clock meets the holdover exit conditions, holdover is exited and the active clock will continue to be used as a reference until another input clock switch event. PLL1 DLD must go high in between input clock switching events."
STATUS_CLKin1(1) | STATUS_CLKin0 | ACTIVE CLOCK |
---|---|---|
X | 1 | CLKin0 |
1 | 0 | CLKin1 |
0 | 0 | Reserved |
Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed tuning voltage is set on CPout1 to operate PLL1 in open loop.
Program HOLDOVER_MODE to enable holdover mode. Holdover mode can be manually enabled by programming the FORCE_HOLDOVER bit.
The holdover mode can be set to operate in 2 different sub-modes.
Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector frequency divided by DAC_CLK_DIV. These updates occur any time EN_TRACK = 1.
The DAC update rate should be programmed for <= 100 kHz to ensure DAC holdover accuracy.
When tracking is enabled the current voltage of DAC can be readback, see DAC_CNT.
The holdover mode is entered as described in Input Clock Switching. Typically this is because:
PLL1 is run in open loop mode.
The HOLDOVER status signal can be monitored on the Status_HOLDOVER or Status_LD pin by programming the HOLDOVER_MUX or LD_MUX register to Holdover Status.
Holdover mode can be exited in one of two ways.
To exit holdover by programming, set HOLDOVER_MODE = Disabled. HOLDOVER_MODE can then be re-enabled by programming HOLDOVER_MODE = Enabled. Care should be taken to ensure that the active clock upon exiting holdover is as expected, otherwise the CLKin_SELECT_MODE register may need to be re-programmed.
When in holdover mode, PLL1 runs in open loop and the DAC sets the CPout1 voltage. If Fixed CPout1 mode is used, then the output of the DAC is a voltage dependant upon the MAN_DAC register. If Tracked CPout1 mode is used, then the output of the DAC is the voltage at the CPout1 pin before holdover mode was entered. When using Tracked mode and EN_MAN_DAC = 1, during holdover the DAC value is loaded with the programmed value in MAN_DAC, not the tracked value.
When in Tracked CPout1 mode, the DAC has a worst case tracking error of ±2 LSBs once PLL1 tuning voltage is acquired. The step size is approximately 3.2 mV; therefore, the VCXO frequency error during holdover mode caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use. Therefore, the accuracy of the system when in holdover mode in ppm is:
Example: Consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The accuracy of the system in holdover in ppm is:
It is important to account for this frequency error when determining the allowable frequency error window to cause holdover mode to exit.
The LMK04208 device can be programmed to automatically exit holdover mode when the accuracy of the frequency on the active clock input achieves a specified accuracy. The programmable variables include PLL1_WND_SIZE and DLD_HOLD_CNT.
See Digital Lock Detect Frequency Accuracy to calculate the register values to cause holdover to automatically exit upon reference signal recovery to within a user specified ppm error of the holdover frequency.
It is possible for the time to exit holdover to vary because the condition for automatic holdover exit is for the reference and feedback signals to have a time/phase error less than a programmable value. Because it is possible for two clock signals to be very close in frequency but not close in phase, it may take a long time for the phases of the clocks to align themselves within the allowable time/phase error before holdover exits.
The maximum phase detector frequency (fPD1) of PLL1 is 40 MHz. Since a narrow loop bandwidth should be used for PLL1, the need to operate at high phase detector rate to lower the in-band phase noise becomes unnecessary. The maximum values for the PLL1 R and N dividers is 16,383. Charge pump current ranges from 100 to 1600 µA. PLL1 N divider may be driven by OSCin port through the OSCout_MUX output (default) or by internal or external feedback as selected by Feedback Mux in 0-delay mode.
Low charge pump currents and phase detector frequencies aid design of low loop bandwidth loop filters with reasonably sized components to allow the VCXO or PLL2 to dominate phase noise inside of PLL2 loop bandwidth. High charge pump currents may be used by PLL1 when using VCXOs with leaky tuning voltage inputs to improve system performance.
PLL2's maximum phase detector frequency (fPD2) is 155 MHz. Operating at highest possible phase detector rate will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter. The in-band phase noise from the reference input and PLL is proportional to N2. The maximum value for the PLL2 R divider is 4,095. The maximum value for the PLL2 N divider is 262,143. The N2 Prescaler in the total N feedback path can be programmed for values 2 to 8 (all divides even and odd). Charge pump current ranges from 100 to 3200 µA.
High charge pump currents help to widen the PLL2 loop bandwidth to optimize PLL2 performance.
The PLL2 reference input at the OSCin port may be routed through a frequency doubler before the PLL2 R Divider. The frequency doubler feature allows the phase comparison frequency to be increased when a relatively low frequency oscillator is driving the OSCin port. By doubling the PLL2 phase detector frequency, the in-band PLL2 noise is reduced by about 3 dB.
When using the doubler, PLL2 R Divider may be used to reduce the phase detector frequency to the limit of the PLL2 maximum phase detector frequency.
For applications in which the OSCin frequency and PLL2 phase detector frequency are equal, the best PLL2 in-band noise can be achieved when the doubler is enabled (EN_PLL2_REF_2X = 1) and the PLL2 R divide value is 2. Do not use doubler disabled (EN_PLL2_REF_2X = 0) and PLL2 R divide value of 1.
Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count reaches a user specified value lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be asserted false. This is illustrated in Figure 10.
The incremental lock detect count feature functions as a digital filter to ensure that lock detect is not asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock.
The digital lock detect signal can be monitored on the Status_LD or Status_Holdover pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.
See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect.
The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Holdover Mode for more info.
The Status_LD, Status_HOLDOVER, Status_CLKin0, Status_CLKin1, and SYNC pins can be programmed to output a variety of signals for indicating various statuses like digital lock detect, holdover, several DAC indicators, and several PLL divider outputs.
This is a very simple output. In combination with the output _MUX register, this output can be toggled between high and low. Useful to confirm MICROWIRE programming or as a general purpose IO.
PLL1 DLD, PLL2 DLD, and PLL1 + PLL2 are selectable on certain output pins. See Digital Lock Detect for more information.
Indicates if the device is in Holdover mode. See HOLDOVER_MODE for more information.
Various flags for the DAC can be monitored including DAC Locked, DAC Rail, DAC Low, and DAC High.
When the PLL1 tuning voltage crosses the low threshold, DAC Low is asserted. When PLL1 tuning voltage crosses the high threshold, DAC High is asserted. When either DAC Low or DAC High is asserted, DAC Rail will also be asserted.
DAC Locked is asserted when EN_Track = 1 and DAC is closely tracking the PLL1 tuning voltage.
The PLL divider outputs are useful for debugging failure to lock issues. It allows the user to measure the frequency the PLL inputs are receiving. The settings of PLL1_R, PLL1_N, PLL2_R, and PLL2_N output pulses at the phase detector rate. The settings of PLL1_R / 2, PLL1_N / 2, PLL2_R / 2, and PLL2_N / 2 output a 50% duty cycle waveform at half the phase detector rate.
The clock input loss of signal indicator is asserted when LOS is enabled (EN_LOS) and the clock no longer detects an input as defined by the time-out threshold, LOS_TIMEOUT.
If this clock is the currently selected/active clock, this pin will be asserted.
The readback data can be output on any pin programmable to readback mode. For more information on readback see Readback.
The integrated VCO uses a frequency calibration routine when register R30 is programmed to lock VCO to target frequency. Register R30 contains the PLL2_N register.
During the frequency calibration the PLL2_N_CAL value is used instead of PLL2_N, this allows 0-delay modes to have a separate PLL2 N value for VCO frequency calibration and regular operation. See Register 29, Register 30, and PLL Programming for more information.
This section discussing Fixed Digital delay and associated registers is fundamental to understanding digital delay and dynamic digital delay.
Clock outputs may be delayed or advanced from one another by up to 517.5 clock distribution path periods. By programming a digital delay value from 4.5 to 522 clock distribution path periods, a relative clock output delay from 0 to 517.5 periods is achieved. The CLKoutX_DDLY (5 to 522) and CLKoutX_HS (–0.5 or 0) registers set the digital delay as shown in Table 3.
CLKoutX_DDLY | CLKoutX_HS | DIGITAL DELAY |
---|---|---|
5 | 1 | 4.5 |
5 | 0 | 5 |
6 | 1 | 5.5 |
6 | 0 | 6 |
7 | 1 | 6.5 |
7 | 0 | 7 |
... | ... | ... |
520 | 0 | 520 |
521 | 1 | 520.5 |
521 | 0 | 521 |
522 | 1 | 521.5 |
522 | 0 | 522 |
NOTE
Digital delay values only take effect during a SYNC event and if the NO_SYNC_CLKoutX bit is cleared for this clock group. See Clock Output Synchronization (SYNC) for more information.
The resolution of digital delay is determined by the frequency of the clock distribution path. The clock distribution path is the output of Mode Mux1 (Functional Block Diagram). The best resolution of digital delay is achieved by bypassing the VCO divider.
The digital delay between clock outputs can be dynamically adjusted with no or minimum disruption of the output clocks. See Dynamically Programming Digital Delay for more information.
Given a VCO frequency of 2949.12 MHz and no VCO divider, by using digital delay the outputs can be adjusted in 1 / (2 * 2949.12 MHz) = ~169.54 ps steps.
To achieve quadrature (90 degree shift) between the 122.88-MHz outputs on CLKout4 and CLKout6 from a VCO frequency of 2949.12 MHz and bypassing the VCO divider, consider the following:
This result in the following programming:
Table 4 shows some of the possible phase delays in degrees achievable in the above example.
CLKout3_DDLY | CLKout3_HS | RELATIVE DIGITAL DELAY | DEGREES of 122.88 MHz |
---|---|---|---|
5 | 1 | -0.5 | -7.5° |
5 | 0 | 0.0 | 0° |
6 | 1 | 0.5 | 7.5° |
6 | 0 | 1.0 | 15.0° |
7 | 1 | 1.5 | 22.5° |
7 | 0 | 2.0 | 30.0° |
8 | 1 | 2.5 | 37.5° |
8 | 0 | 3.0 | 45.0° |
9 | 1 | 3.5 | 52.5° |
9 | 0 | 4.0 | 60.0° |
10 | 1 | 4.5 | 67.5° |
10 | 0 | 5.0 | 75.0° |
11 | 1 | 5.5 | 82.5° |
11 | 0 | 6.0 | 90.0° |
12 | 1 | 6.5 | 97.5° |
12 | 0 | 7.0 | 105.0° |
13 | 1 | 7.5 | 112.5° |
13 | 0 | 8.0 | 120.0° |
14 | 1 | 8.5 | 127.5° |
... | ... | ... | ... |
Figure 12 illustrates clock outputs programmed with different digital delay values during a SYNC event.
Refer to Dynamically Programming Digital Delay for more information on dynamically adjusting digital delay.
The purpose of the SYNC function is to synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC. SYNC can also be used to hold the outputs in a low or 0 state. The NO_SYNC_CLKoutX bits can be set to disable synchronization for a clock group.
To enable SYNC, EN_SYNC must be set. See EN_SYNC, Enable Synchronization.
The digital delay value set by CLKoutX_DDLY takes effect only upon a SYNC event. The digital delay due to CLKoutX_HS takes effect immediately upon programming. See Dynamically Programming Digital Delay for more information on dynamically changing digital delay.
During a SYNC event, clock outputs driven by the VCO are not synchronized to clock outputs driven by OSCin. OSCout is always driven by OSCin. CLKout3 or CLKout4 may be driven by OSCin depending on the CLKoutX_OSCin_Sel bit value. While SYNC is asserted, NO_SYNC_CLKoutX operates normally for CLKout3 or CLKout4 under all circumstances. SYNC operates normally for CLKout3 or CLKout4 when driven by VCO.
When SYNC is asserted, the outputs to be synchronized are held in a logic low state. When SYNC is unasserted, the clock outputs to be synchronized are activated and will transition to a high state simultaneously with one another except where different digital delay values have been programmed.
Refer to Dynamically Programming Digital Delay for SYNC functionality when SYNC_QUAL = 1.
SYNC_TYPE | SYNC_POL _INV |
SYNC PIN | CLOCK OUTPUT STATE |
---|---|---|---|
0,1,2 (Input) | 0 | 0 | Active |
0,1,2 (Input) | 0 | 1 | Low |
0,1,2 (Input) | 1 | 0 | Low |
0,1,2 (Input) | 1 | 1 | Active |
3, 4, 5, 6 (Output) | 0 | 0 or 1 | Active |
3, 4, 5, 6 (Output) | 1 | 0 or 1 | Low |
There are five methods to generate a SYNC event:
NOTE
Due to the speed of the clock distribution path (as fast as ~325 ps period) and the slow slew rate of the SYNC, the exact VCO cycle at which the SYNC is asserted or unasserted by the SYNC is undefined. The timing diagrams show a sharp transition of the SYNC to clarify functionality.
Any CLKout groups that have their NO_SYNC_CLKoutX bits set will be unaffected by the SYNC event. It is possible to perform a SYNC operation with the NO_SYNC_CLKoutX bits cleared, then set the NO_SYNC_CLKoutX bits so that the selected clocks will not be affected by a future SYNC. Future SYNC events will not effect these clocks but will still cause the newly synchronized clocks to be re-synchronized using the currently programmed digital delay values. When this happens, the phase relationship between the first group of synchronized clocks and the second group of synchronized clocks will be undefined unless the SYNC pulse is qualified by an output clock. See Dynamically Programming Digital Delay.
When discussing the timing of the SYNC function, one cycle refers to one period of the clock distribution path.
Refer to Figure 11 during this discussion on the timing of SYNC. SYNC must be asserted for greater than one clock cycle of the clock distribution path to latch the SYNC event. After SYNC is asserted, the SYNC event is latched on the rising edge of the distribution path clock, at time A. After this event has been latched, the outputs will not reflect the low state for 6 cycles, at time B. Due to the asynchronous nature of SYNC with respect to the output clocks, it is possible that a glitch pulse could be created when the clock output goes low from the SYNC event. This is shown by CLKout4 in Figure 11 and CLKout2 in Figure 12. See Relative Dynamic Digital Delay for more information on synchronizing relative to an output clock to eliminate or minimize this glitch pulse.
After SYNC becomes unasserted the event is latched on the following rising edge of the distribution path clock, time C. The clock outputs will rise at time D, coincident with a rising distribution clock edge that occurs after 6 cycles plus as many more cycles as programmed by the digital delay for that clock output. Therefore, the soonest a clock output will become high is 11 cycles after the SYNC unassertion event registration, time C, when the smallest digital delay value of 5 is set. If CLKoutX_HS = 1 and CLKoutX_DDLY = 5, then the clock output will rise 10.5 cycles after SYNC is unassertion event registration.
Figure 12 illustrates the timing with different digital delays programmed.
To use dynamic digital delay synchronization qualification set SYNC_QUAL = 1. This causes the SYNC pulse to be qualified by a clock output so that the SYNC event occurs after a specified time from a clock output transition. This allows the relative adjustment of clock output phase in real-time with no or minimum interruption of clock outputs. Hence the term "dynamic digital delay."
Note that changing the phase of a clock output requires momentarily altering in the rate of change of the clock output phase and therefore by definition results in a frequency distortion of the signal.
Without qualifying the SYNC with an output clock, the newly synchronized clocks would have a random and unknown digital delay (or phase) with respect to clock outputs not currently being synchronized.
The clock used for qualification of SYNC is selected with the feedback mux (FEEDBACK_MUX).
If the clock selected by the feedback mux has its NO_SYNC_CLKoutX = 1, then an absolute dynamic digital delay adjustment will be performed during a SYNC event and the digital delay of the feedback clock will not be adjusted.
If the clock selected by the feedback mux has its NO_SYNC_CLKoutX = 0, then a self-referenced or relative dynamic digital delay adjustment will be performed during a SYNC event and the digital delay of the feedback clock will be adjusted.
Clocks with NO_SYNC_CLKoutX = 1 always operate without interruption.
When using a 0-delay mode absolute dynamic digital delay is recommended. Using relative dynamic digital delay with a 0-delay mode may result in a momentary clock loss on the adjusted clock also being used for 0-delay feedback that may result in PLL1 DLD becoming low. This may result in HOLDOVER mode being activated depending upon device configuration.
The minimum step size adjustment for digital delay is half a clock distribution path cycle. This is achieved by using the CLKoutX_HS bit. The CLKoutX_HS bit change effect is immediate without the need for SYNC. To shift digital delay using CLKoutX_DDLY a SYNC signal must be generated for the change to take effect.
To dynamically adjust the digital delay with respect to an existing clock output the device should be programmed as follows:
To dynamically adjust digital delay a SYNC must occur. Once the SYNC is qualified by an output clock, 3 cycles later an internal one shot pulse will occur. The width of the one shot pulse is 3 cycles. This internal one shot pulse will cause the outputs to turn off and then back on with a fixed delay with respect to the falling edge of the qualification clock. This allows for dynamic adjustments of digital delay with respect to an output clock.
The qualified SYNC timing is shown in Figure 13 for absolute dynamic digital delay and Figure 14 for relative dynamic digital delay.
When adjusting digital delay dynamically, the falling edge of the qualifying clock selected by the FEEDBACK_MUX must coincide with the falling edge of the clock distribution path. For this requirement to be met, program the CLKoutX_HS value of the qualifying clock group according to Table 6.
DISTRIBUTION PATH FREQUENCY | CLKoutX_DIV VALUE | CLKoutX_HS |
---|---|---|
≥ 1.8 GHz | Even | Must = 1 during SYNC event. |
Odd | Must = 0 during SYNC event. | |
< 1.8 GHz | Even | Must = 0 during SYNC event. |
Odd | Must = 1 during SYNC event. |
Absolute dynamic digital delay can be used to program a clock output to a specific phase offset from another clock output.
Pros:
Cons:
To illustrate the absolute dynamic digital delay adjust procedure, consider the following example.
System Requirements:
The application requires the 491.52 MHz clock to be stepped in 30 degree steps (~169.5 ps), which is the minimum step resolution allowable by the clock distribution path requiring use of the half step bit (CLKoutX_HS). That is 1 / 2949.52 MHz / 2 = ~169.5 ps. During the stepping of the 491.52-MHz clock, the 983.04-MHz and 245.76-MHz clock must not be interrupted.
REGISTER | PURPOSE |
---|---|
SYNC_QUAL = 1 | Use a clock output for qualifying the SYNC pulse for dynamically adjusting digital delay. |
EN_SYNC = 1 (default) | Required for SYNC functionality. |
CLKout2_PD = 0 | Required when SYNC_QUAL = 1. CLKout2 may be powered down or in use. |
EN_FEEDBACK_MUX = 1 | Enable the feedback mux for SYNC operation for dynamically adjusting digital delay. |
FEEDBACK_MUX = 2 (CLKout2) | Use the fixed 245.76-MHz clock as the SYNC qualification clock. |
NO_SYNC_CLKout0 = 1 | This clock output (983.04 MHz) won't be affected by SYNC. It will always operate without interruption. |
NO_SYNC_CLKout2 = 1 | This clock output (245.76 MHz) won't be affected by SYNC. It will always operate without interruption. This clock will also be the qualifying clock in this example. |
CLKout2_HS = 1 | Since CLKout2 is the qualifying clock and CLKoutX_DIV is even, the half step bit must be set to 1. See Table 6. |
SYNC_EN_AUTO = 1 | Automatic generation of SYNC is allowed for this case. |
After the registers in Table 7 have been programmed, the application may now dynamically adjust the digital delay of CLKout1 (491.52 MHz).
Refer to Table 8 for the programming values to set a specified phase offset from the absolute reference clock. Table 8 is dependant upon the qualifying clock divide value of 12, refer to Calculating Dynamic Digital Delay Values for Any Divide for information on creating tables for any divide value.
DEGREES OF ADJUSTMENT FROM INITIAL 491.52 MHz PHASE | PROGRAMMING | |
---|---|---|
±0 or ±360 degrees | CLKout1_DDLY = 7; CLKout1_HS = 1 | |
30 degrees | –330 degrees | CLKout1_DDLY = 7; CLKout1_HS = 0 |
60 degrees | –300 degrees | CLKout1_DDLY = 8; CLKout1_HS = 1 |
90 degrees | –270 degrees | CLKout1_DDLY = 8; CLKout1_HS = 0 |
120 degrees | –240 degrees | CLKout1_DDLY = 9; CLKout1_HS = 1 |
150 degrees | –210 degrees | CLKout1_DDLY = 9; CLKout1_HS = 0 |
180 degrees | –180 degrees | CLKout1_DDLY = 10; CLKout1_HS = 1 |
210 degrees | –150 degrees | CLKout1_DDLY = 10; CLKout1_HS = 0 |
240 degrees | –120 degrees | CLKout1_DDLY = 5; CLKout1_HS = 1 |
270 degrees | –90 degrees | CLKout1_DDLY = 5; CLKout1_HS = 0 |
300 degrees | –60 degrees | CLKout1_DDLY = 6; CLKout1_HS = 1 |
330 degrees | –30 degrees | CLKout1_DDLY = 6; CLKout1_HS = 0 |
After setting the new digital delay values, the act of programming R1 will start a SYNC automatically because SYNC_EN_AUTO = 1.
If the user elects to reduce the number of SYNCs because they are not required when only CLKout1_HS is set, then SYNC_EN_AUTO is = 0 and the SYNC may now be generated by toggling the SYNC pin or by toggling the SYNC_POL_INV bit. Because of the internal one shot pulse, no strict timing of the SYNC pin or SYNC_POL_INV bit is required.
After the SYNC event, the clock output will adjust according to Table 8. See Figure 13 for a detailed view of the timing diagram. The timing diagram critical points are:
Relative dynamic digital delay can be used to program a clock output to a specific phase offset from another clock output.
Pros:
Cons:
To illustrate the relative dynamic digital delay adjust procedure, consider the following example.
System Requirements:
The application requires the 491.52-MHz clock to be stepped in 30 degree steps (~169.5 ps), which is the minimum step resolution allowable by the clock distribution path. That is 1 / 2949.52 MHz / 2 = ~169.5 ps. During the stepping of the 491.52 MHz clocks the 983.04 MHz clock must not be interrupted.
REGISTER | PURPOSE |
---|---|
SYNC_QUAL = 1 | Use clock output for qualifying the SYNC pulse for dynamically adjusting digital delay. |
EN_SYNC = 1 (default) | Required for SYNC functionality. |
CLKout2_PD = 0 | Required when SYNC_QUAL = 1. CLKout4 and/or CLKout5 outputs may be powered down or in use. |
EN_FEEDBACK_MUX = 1 | Enable the feedback mux for SYNC operation for dynamically adjusting digital delay. |
FEEDBACK_MUX = 1 (CLKout1) | Use the clock itself as the SYNC qualification clock. |
NO_SYNC_CLKout0 = 1 | This clock output (983.04 MHz) won't be affected by SYNC. It will always operate without interruption. |
NO_SYNC_CLKout2 = 1 | CLKout3’s phase is not to change with respect to CLKout0. |
SYNC_EN_AUTO = 0 (default) | Automatic generation of SYNC is not allowed because of the half step requirement in relative dynamic digital delay mode. SYNC must be generated manually by toggling the SYNC_POL_INV bit or the SYNC pin. |
After the above registers have been programmed, the application may now dynamically adjust the digital delay of the 491.52 MHz clocks.
Refer to Table 10 for the programming sequence to step one half clock distribution period forward or backwards. Refer to Calculating Dynamic Digital Delay Values for Any Divide for more information on how to calculate digital delay and half step values for other cases.
To fulfill the qualifying clock output half step requirement in Table 6 when dynamically adjusting digital delay, the CLKoutX_HS bit must be cleared for clocks with even divides. So before any dynamic digital delay adjustment, CLKoutX_HS must be clear because the clock divide value is even. To achieve the final required digital delay adjustment, the CLKoutX_HS bit may set after SYNC.
STEP DIRECTION and CURRENT HS STATE | PROGRAMMING SEQUENCE |
---|---|
Adjust clock output one step forward. CLKout1_HS is 0. |
1. CLKout1_HS = 1. |
Adjust clock output one step forward. CLKout1_HS is 1. |
1. CLKout1_DDLY = 9. 2. Perform SYNC event. 3. CLKout1_HS = 0. |
Adjust clock output one step backward. CLKout1_HS is 0. |
1. CLKout1_HS = 1. 2. CLKout1_DDLY = 5. 3. Perform SYNC event. |
Adjust clock output one step backward. CLKout1_HS is 1. |
1. CLKout1_HS = 0. |
After programing the updated CLKout1_DDLY and CLKout1_HS values, perform a SYNC event. The SYNC may be generated by toggling the SYNC pin or by toggling the SYNC_POL_INV bit. Because of the internal one shot pulse, no strict timing of the SYNC pin or SYNC_POL_INV bit is required. After the SYNC event, the clock output will be at the specified phase. See Figure 14 for a detailed view of the timing diagram. The timing diagram critical points are:
When 0-delay mode is enabled the clock output selected by the Feedback Mux is connected to the PLL1 N counter to ensure a fixed phase relationship between the selected CLKin and the fed back CLKout. When all the clock outputs are synced together, all the clock outputs will share the same fixed phase relationship between the selected CLKin and the fed back CLKout. The feedback can be internal or external using FBCLKin port.
When 0-delay mode is enabled the lowest frequency clock output is fed back to the Feedback Mux to ensure a repeatable fixed CLKin to CLKout phase relationship between all clock outputs.
If a clock output that is not the lowest frequency output is selected for feedback, then clocks with lower frequencies will have an unknown phase relationship with respect the other clocks and clock input. There will be a number of possible phase relationships equal to Feedback_Clock_Frequency / Lower_Clock_Frequency that may occur.
The Feedback Mux selects the even clock output of any clock group for internal feedback or the FBCLKin port for external 0-delay feedback. The even clock can remain powered down as long as the CLKoutX_PD bit is = 0 for its clock group.
To use 0-delay mode, the bit EN_FEEDBACK_MUX must be set (=1) to power up the feedback mux.
When using an external VCO mode, internal 0-delay feedback must be used since the FBCLKin port is shared with the Fin input.
See PLL Programming for more information on programming the various PLL and output dividers for 0-delay mode.
Table 11 outlines several registers to program for 0-delay mode.
REGISTER | PURPOSE |
---|---|
MODE = 2, 5, or 8 | Select one of the 0-delay modes: Dual PLL, Internal VCO Dual PLL, External VCO Single PLL, Internal VCO |
EN_FEEDBACK_MUX = 1 | Enable feedback mux. |
FEEDBACK_MUX = Application Specific | Select CLKout or FBCLKin for 0-delay feedback. |
CLKoutX_DIV | The divide value of the clock selected by FEEDBACK_MUX is important for PLL1_N or PLL2_N value calculation for Dual PLL or Single PLL mode respectively. |
PLL1_N or PLL2_N | PLL1_N or PLL2_N value used with CLKoutX_DIV in loop for Dual PLL or Single PLL mode respectively. |
The LMK04208 is capable of operating in several different modes as programmed by MODE: Device Mode.
MODE R11[31:27] |
PLL1 | PLL2 | PLL2 VCO | 0-DELAY | CLOCK DIST |
---|---|---|---|---|---|
0 | X | X | Internal | X | |
2 | X | X | Internal | X | X |
3 | X | X | External | X | |
5 | X | X | External | X | X |
6 | X | Internal | X | ||
8 | X | Internal | X | X | |
11 | X | External | X | ||
16 | X |
In addition to selecting the device's mode of operation above, some modes require additional configuration. Also there are other features including holdover and dynamic digital delay that can also be enabled.
REGISTER | HOLDOVER | 0-DELAY | DYNAMIC DIGITAL DELAY |
---|---|---|---|
HOLDOVER_MODE | 2 | — | — |
EN_TRACK | User | — | — |
DAC_CLK_DIV | User | — | — |
EN_MAN_DAC | User | — | — |
DISABLE_DLD1_DET | User | — | — |
EN_VTUNE_RAIL_DET | User | — | — |
DAC_HIGH_TRIP | User | — | — |
DAC_LOW_TRIP | User | — | — |
FORCE_HOLDOVER | 0 | — | — |
SYNC_EN_AUTO | — | — | User |
SYNC_QUAL | — | — | 1 |
EN_SYNC | — | — | 1 |
CLKout2_PD | — | — | 0 |
EN_FEEDBACK_MUX | — | 1 | 1 |
FEEDBACK_MUX | — | Feedback Clock | Qualifying Clock |
NO_SYNC_CLKoutX | — | — | User |
The LMK04208 is a flexible device that can be configured for many different use cases. The following simplified block diagrams help show the user the different use cases of the device.
Figure 15 illustrates the typical use case of the LMK04208 in dual loop mode. In dual loop mode the reference to PLL1 is either CLKin0 or CLKin1. An external VCXO or tunable crystal will be used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO or low cost tunable crystal by using a narrow loop bandwidth. The VCXO or tunable crystal output may be buffered through the OSCout port and optionally on up to 2 of the CLKouts. The VCXO or tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to six divide/delay blocks which drive 12 clock outputs.
Holdover functionality is optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of PLL1 to the VCXO or tunable crystal.
It is also possible to use an external VCO in place of PLL2's internal VCO.
Figure 16 and Figure 17 illustrate the use case of 0-delay dual loop mode. This configuration is very similar to Dual PLL except that the feedback to the first PLL is driven by a clock output. 0-Delay causes one clock output to have deterministic phase with respect to the clock input. Since all the clock outputs can be synchronized together, all the clock outputs can be in phase with the clock input signal.
When the internal VCO is used, the feedback to PLL1 can be connected internally as shown or externally using FBCLKin (CLKin1) as an input port. When an external VCO is used, the feedback to PLL1 must be connected internally since the external VCO drives the Fin (CLKin1) port and thus precludes the use of external feedback via FBCLKin.
It is also possible to use an external VCO in place of PLL2's internal VCO.
Figure 18 illustrates the use case of single PLL mode. In single PLL mode only PLL2 is used and PLL1 is powered down. OSCin is used as the reference input. The internal VCO drives up to 6 divide/delay blocks which drive 12 clock outputs. The reference at OSCin can be used to the OSCout port. OSCin can also optionally drive up to 2 of the clock outputs.
It is also possible to use an external VCO in place of PLL2's internal VCO.
Figure 19 illustrates the use case of 0-delay single PLL mode. This configuration is very similar to Single PLL except that the feedback to PLL2 comes from a clock output. This causes the clock outputs to be in phase with the reference input. Since all the clock outputs can be synchronized together, all the clock outputs can be in phase with the clock input signal. The feedback to PLL2 can be performed internally as shown, or externally using FBCLKin (CLKin1) as an input port.
It is also possible to use an external VCO in place of PLL2's internal VCO.
Figure 20 illustrates the LMK04208 used for clock distribution. CLKin1 is used to drive up to 6 divide/delay blocks which drive 12 outputs. OSCin can be used to drive the OSCout port. OSCin can also optionally drive up to 2 of the clock outputs.
LMK04208 devices are programmed using 32-bit registers. Each register consists of a 5-bit address field and 27-bit data field. The address field is formed by bits 0 through 4 (LSBs) and the data field is formed by bits 5 through 31 (MSBs). The contents of each register is clocked in MSB first (bit 31), and the LSB (bit 0) last. During programming, the LEuWire signal should be held low. The serial data is clocked in on the rising edge of the CLKuWire signal. After the LSB (bit 0) is clocked in the LEuWire signal should be toggled low-to-high-to-low to latch the contents into the register selected in the address field. TI recommends programming registers in numeric order, for example R0 to R16, and R24 to R31 to achieve proper device operation. Figure 1 illustrates the serial data timing sequence.
To achieve proper frequency calibration, the OSCin port must be driven with a valid signal before programming register R30. Changes to PLL2 R divider or the OSCin port frequency require register R30 to be reloaded in order to activate the frequency calibration process.
A slew rate of at least 30 V/us is recommended for MICROWIRE signals.
After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during programming of the other devices.
At no time should the MICROWIRE registers be programmed to any value other than what is specified in the datasheet.
In some cases when programming register R0 to R5 to change the CLKoutX_DIV divide value or CLKoutX_DDLY delay value, 3 additional CLKuWire cycles must occur after loading the register for the newly programmed divide or delay value to take effect. These special cases include:
Also, since SYNC_EN_AUTO bit = 1 automatically generates a SYNC on the falling edge of LE when R0 to R5 is programmed, further programming considerations must be made when SYNC_EN_AUTO = 1.
These special programming cases requiring the additional three clock cycles may be properly programmed by one of the following methods shown in Table 14.
CLKoutX_DIV and CLKoutX_DDLY |
SYNC_EN_AUTO | PROGRAMMING METHOD |
---|---|---|
CLKoutX_DIV ≤ 25 and CLKoutX_DDLY ≤ 12 |
0 or 1 | No Additional Clocks Required (Normal) |
CLKoutX_DIV > 25 or CLKoutX_DDLY > 12 |
0 | Three Extra CLKuWire Clocks (Or program another register) |
CLKoutX_DIV > 25 or CLKoutX_DDLY > 12 |
1 | Three Extra CLKuWire Clocks while LEuWire is High |
In this example, all registers have been programmed, the PLLs are locked. An LMK04208 has been generating a clock output frequency of 61.44 MHz on CLKout4 using a VCO frequency of 2949.12 MHz and a divide value of 48. SYNC_EN_AUTO = 0. At a later time the application requires a 30.72-MHz output on CLKout4. By reprogramming register R4 with CLKout4_DIV = 96 twice, the divide value of 96 is set for clock output 4 which results in an output frequency of 30.72 MHz (2949.12 MHz / 96 = 30.72 MHz) on CLKout4.
In this example, the required 3 CLKuWire cycles were achieved by reprogramming the R4 register with the same value twice.
Registers are programmed in numeric order with R0 being the first and R31 being the last register programmed. The recommended programming sequence involves programming R0 with the reset bit (b17) set to 1 to ensure the device is in a default state. If R0 is programmed again, the reset bit must be cleared to 0 during the programming of R0.
Readback from the MICROWIRE programming registers is available. The MICROWIRE readback function can be enabled on the Status_LD, Status_HOLDOVER, Status_CLKin0, Status_CLKin1, or SYNC pin by programming the corresponding MUX register to “uWire Readback” and the corresponding TYPE register to "Output (push-pull)." Power on reset defaults the Status_HOLDOVER pin to “uWire Readback.”
For timing specifications, see Timing Requirements. Figure 4 shows timing for LEuWire for both READBACK_LE = 1 and 0. The rising edges of CLKuWire during MICROWIRE readback continue to clock data on DATAuWire into the device during readback. If after the readback, LEuWire transitions from low to high, this data will be latched to the decoded register. The decoded register address consists of the last 5 bits clocked on DATAuWire as shown in Figure 4.
NOTE
For debug of the MICROWIRE interface, TI recommends simply programming an output pin mux to active low and then toggle the output type register between output and inverting output while observing the output pin for a low to high transition. For example, to verify MICROWIRE programming, set the LD_MUX = 0 (Low) and then toggle the LD_TYPE register between 3 (Output, push-pull) and 4 (Output inverted, push-pull). The result will be that the Status_LD pin will toggle from low to high.
To perform a readback operation first set the register to be read back by programming the READBACK_ADDR register. Then after any MICROWIRE write operation, with the LEuWire pin held low continue to clock the CLKuWire pin. On every rising edge of the CLKuWire pin a new data bit is clocked onto the any pins programmed for uWire Readback. If the READBACK_LE bit is set, the LEuWire pin should be left high after LEuWire rising edge while continuing to clock the CLKuWire pin.
It is allowable to perform a register read back in the same MICROWIRE operation which set the READBACK_ADDR register value.
Figure 4 illustrates the serial data timing sequence for a readback operation for both cases of READBACK_LE = 0 (POR default) and READBACK_LE = 1.
Data is clocked out MSB first. After 27 clocks all the data values will have been read and the read operation is complete. If READBACK_LE = 1, the LEuWire line may now be lowered. It is allowable for the CLKuWire pin to be clocked additional cycles, but the data on the readback pin will be invalid. CLKuWire must be low before the falling edge of LEuWire.
To readback register R3 perform the following steps:
Table 15 provides the register map for device programming. Normally any register can be read from the same data address it is written to. However, READBACK_LE has a different readback address. Also, the DAC_CNT register is a read only register. Table 16 shows the address for READBACK_LE and DAC_CNT. Bits marked as reserved are undefined upon readback.
Observe that only the DATA bits are readback during a readback which can result in an offset of 5 bits between the two register tables.
REG- ISTER |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Data [26:0] | Address [4:0] | |||||||||||||||||||||||||||||||
R0 | CLKout 0_PD | 0 | CLKout0 _ADLY_SEL |
CLKout0_DDLY [27:18] | RESET | CLKout 0_HS | CLKout0_DIV [15:5] | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||
R1 | CLKout 1_PD | 0 | CLKout1 _ADLY_SEL |
CLKout1_DDLY [27:18] | POWERDOWN | CLKout 1_HS | CLKout1_DIV [15:5] | 0 | 0 | 0 | 0 | 1 | ||||||||||||||||||||
R2 | CLKout 2_PD | 0 | CLKout2 _ADLY_SEL |
CLKout2_DDLY [27:18] | 0 | CLKout 2_HS | CLKout2_DIV [15:5] | 0 | 0 | 0 | 1 | 0 | ||||||||||||||||||||
R3 | CLKout 3_PD | CLKout3_ OSCin_Sel | CLKout3 _ADLY_SEL |
CLKout3_DDLY [27:18] | 0 | CLKout 3_HS | CLKout3_DIV [15:5] | 0 | 0 | 0 | 1 | 1 | ||||||||||||||||||||
R4 | CLKout 4_PD | CLKout4_ OSCin_Sel | CLKout4 _ADLY_SEL |
CLKout4_DDLY [27:18] | 0 | CLKout 4_HS | CLKout4_DIV [15:5] | 0 | 0 | 1 | 0 | 0 | ||||||||||||||||||||
R5 | CLKout 5_PD | 0 | CLKout5 _ADLY_SEL |
CLKout5_DDLY [27:18] | 0 | CLKout 5_HS | CLKout5_DIV [15:5] | 0 | 0 | 1 | 0 | 1 | ||||||||||||||||||||
R6 | 0 | 0 | 0 | 0 | CLKout1_TYPE [27:24] | CLKout0_TYPE [23:20] | 0 | 0 | 0 | 0 | CLKout1_ADLY [15:11] |
0 | CLKout0_ADLY [9:5] |
0 | 0 | 1 | 1 | 0 | ||||||||||||||
R7 | 0 | 0 | 0 | 0 | CLKout3_TYPE [27:24] | CLKout2_TYPE [23:20] | 0 | 0 | 0 | 0 | CLKout3_ADLY [15:11] |
0 | CLKout2_ADLY [9:5] |
0 | 0 | 1 | 1 | 1 | ||||||||||||||
R8 | 0 | 0 | 0 | 0 | CLKout5_TYPE [27:24] | 0 | 0 | 0 | 0 | CLKout4_TYPE [19:16] | CLKout5_ADLY [15:11] |
0 | CLKout4_ADLY [9:5] |
0 | 1 | 0 | 0 | 0 | ||||||||||||||
R9 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
R10 | 0 | 0 | 0 | 1 | OSCout_TYPE [27:24] | 0 | EN_OSCout | 0 | OSCout_MUX | PD_OSCin | OSCout_DIV [18:16] |
0 | 1 | 0 | VCO_MUX | EN_ FEEDBACK_MUX | VCO_DIV [10:8] |
FEEDBACK _MUX [7:5] |
0 | 1 | 0 | 1 | 0 | |||||||||
R11 | MODE [31:27] | EN_SYNC | NO_SYNC_CLKout5 | NO_SYNC_CLKout4 | NO_SYNC_CLKout3 | NO_SYNC_CLKout2 | NO_SYNC_CLKout1 | NO_SYNC_CLKout0 | SYNC_MUX [19:18] |
SYNC_QUAL | SYNC_POL_INV | SYNC_EN_AUTO | SYNC_TYPE [14:12] |
0 | 0 | 0 | 0 | 0 | 0 | EN_PLL2_XTAL | 0 | 1 | 0 | 1 | 1 | |||||||
R12 | LD_MUX [31:27] | LD_TYPE [26:24] | SYNC_PLL2 _DLD | SYNC_PLL1 _DLD | 0 (1) |
0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EN_TRACK | HOLDOVER _MODE [7:6] |
1 | 0 | 1 | 1 | 0 | 0 | |||||||
R13 | HOLDOVER_MUX [31:27] |
HOLDOVER _TYPE [26:24] |
0 | Status_ CLKin1 _MUX [22:20] |
0 | Status_ CLKin0 _TYPE [18:16] |
DISABLE_ DLD1_DET | Status_ CLKin0 _MUX [14:12] |
CLKin _Select _MODE [11:8] |
CLKin_Sel_INV | 0 | EN_CLKin1 | EN_CLKin0 | 0 | 1 | 1 | 0 | 1 | ||||||||||||||
R14 | LOS_ TIMEOUT [31:30] |
0 | EN_LOS | 0 | Status_ CLKin1 _TYPE [26:24] |
0 | 0 | CLKin1_BUF_TYPE | CLKin0_BUF_TYPE | DAC_HIGH_TRIP [19:14] |
0 | 0 | DAC_LOW_TRIP [11:6] |
EN_VTUNE_ RAIL_DET | 0 | 1 | 1 | 1 | 0 | |||||||||||||
R15 | MAN_DAC [31:22] |
0 | EN_MAN_DAC | HOLDOVER_DLD_CNT [19:6] |
FORCE_ HOLDOVER | 0 | 1 | 1 | 1 | 1 | ||||||||||||||||||||||
R16 | XTAL_ LVL |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
R24 | PLL2_C4_LF [31:28] |
PLL2_C3_LF [27:24] |
0 | PLL2_R4_LF [22:20] |
0 | PLL2_R3_LF [18:16] |
0 | PLL1_N_DLY [14:12] |
0 | PLL1_R_DLY [10:8] |
PLL1_ WND_ SIZE [7:6] |
0 | 1 | 1 | 0 | 0 | 0 | |||||||||||||||
R25 | DAC_CLK_DIV [31:22] | 0 | 0 | PLL1_DLD_CNT [19:6] | 0 | 1 | 1 | 0 | 0 | 1 | ||||||||||||||||||||||
R26 | PLL2_ WND_SIZE [31:30] |
EN_PLL2_ REF_2X | PLL2_ CP_POL | PLL2_CP _GAIN [27:26] |
1 | 1 | 1 | 0 | 1 | 0 | PLL2_DLD_CNT [19:6] |
PLL2_CP_TRI | 1 | 1 | 0 | 1 | 0 | |||||||||||||||
R27 | 0 | 0 | 0 | PLL1_CP_POL | PLL1_CP _GAIN [27:26] |
0 | 0 | CLKin1_ PreR_DIV [23: 22] |
CLKin0_ PreR_DIV [21: 20] |
PLL1_R [19:6] |
PLL1_ CP_TRI | 1 | 1 | 0 | 1 | 1 | ||||||||||||||||
R28 | PLL2_R [31: 20] | PLL1_N [19:6] | 0 | 1 | 1 | 1 | 0 | 0 | ||||||||||||||||||||||||
R29 | 0 | 0 | 0 | 0 | 0 | OSCin_FREQ [26:24] |
PLL2_ FAST_PDF | PLL2_N_CAL [22:5] | 1 | 1 | 1 | 0 | 1 | |||||||||||||||||||
R30 | 0 | 0 | 0 | 0 | 0 | PLL2_P [26:24] | 0 | PLL2_N [22:5] | 1 | 1 | 1 | 1 | 0 | |||||||||||||||||||
R31 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | READBACK _LE | READBACK_ADDR [20:16] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | uWire_LOCK | 1 | 1 | 1 | 1 | 1 |
REG- ISTER |
RD 26 |
RD 25 |
RD 24 |
RD 23 |
RD 22 |
RD 21 |
RD 20 |
RD 19 |
RD 18 |
RD 17 |
RD 16 |
RD 15 |
RD 14 |
RD 13 |
RD 12 |
RD 11 |
RD 10 |
RD 9 |
RD 8 |
RD 7 |
RD 6 |
RD 5 |
RD 4 |
RD 3 |
RD 2 |
RD 1 |
RD 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Data [26:0] | |||||||||||||||||||||||||||
RD R12 |
LD_MUX [26:22] | LD_TYPE [21:19] | SYNC_PLL2_DLD | SYNC_PLL1_DLD | READBACK_LE | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EN_TRACK | HOLDOVER_ MODE [2:1] |
1 | |||||||
RD R23 |
RESERVED [26:24] | DAC_CNT [23:14] | RESERVED [13:0] | ||||||||||||||||||||||||
RD R31 |
RESERVED [26:10] | uWire_LOCK |
Table 17 illustrates the default register settings programmed in silicon for the LMK04208 after power on or asserting the reset bit. Capital X and Y represent numeric values.
GROUP | FIELD NAME | DEFAULT VALUE (DECIMAL) |
DEFAULT STATE | FIELD DESCRIPTION | REGISTER | BIT LOCATION (MSB:LSB) |
---|---|---|---|---|---|---|
Clock Output Control | CLKout0_PD | 1 | PD | Powerdown control for analog and digital delay, divider, and both output buffers | R0 | 31 |
CLKout1_PD | 1 | PD | R1 | |||
CLKout2_PD | 1 | PD | R2 | |||
CLKout3_PD | 0 | Normal | R3 | |||
CLKout4_PD | 0 | Normal | R4 | |||
CLKout5_PD | 1 | PD | R5 | |||
CLKout3_OSCin_Sel | 1 | OSCin | Selects the clock source for a clock group from internal VCO or external OSCin | R3 | 30 | |
CLKout4_OSCin_Sel | 0 | VCO | R4 | 30 | ||
CLKoutX_ADLY_SEL | 0 | None | Add analog delay for clock output | R0 to R5 | 28:29 [2] | |
CLKoutX_DDLY | 0 | 5 | Digital delay value | R0 to R5 | 27:18 [10] | |
RESET | 0 | Not in reset | Performs power on reset for device | R0 | 17 | |
POWERDOWN | 0 | Disabled (device is active) |
Device power down control | R1 | 17 | |
CLKoutX_HS | 0 | No shift | Half shift for digital delay | R0 to R5 | 16 | |
CLKout0_DIV | 25 | Divide-by-25 | Divide for clock outputs | R0 | 15:5 [11] | |
CLKout1_DIV | 25 | Divide-by-25 | R1 | |||
CLKout2_DIV | 25 | Divide-by-25 | R2 | |||
CLKout3_DIV | 1 | Divide-by-1 | R3 | |||
CLKout4_DIV | 25 | Divide-by-25 | R4 | |||
CLKout5_DIV | 25 | Divide-by-25 | R5 | |||
CLKout1_TYPE | 0 | Powerdown | Individual clock output format. Select from LVDS/LVPECL/LVCMOS. | R6 | 27:24 [4] | |
CLKout3_TYPE | 8 | LVCMOS (Norm/Norm) |
R7 | |||
CLKout5_TYPE | 0 | Powerdown | R8 | |||
CLKout0_TYPE | 0 | Powerdown | R6 | 23:20 [4] | ||
CLKout2_TYPE | 0 | Powerdown | R7 | |||
R8 | 19:16 [4] | |||||
CLKout4_TYPE | 1 | LVDS | ||||
CLKoutX_ADLY | 0 | No delay | Analog delay setting for clock group | R6 to R8 | 15:11, 9:5 [5] | |
Osc Buffer Control | OSCout_TYPE | 1 | LVDS | OSCout default clock output | R10 | 27:24 [4] |
EN_OSCout | 1 | Enabled | Enable OSCout output buffer | R10 | 22 | |
OSCout_MUX | 0 | Bypass Divider | Select OSCout divider or bypass | R10 | 20 | |
PD_OSCin | 0 | OSCin powered | Allows OSCin to be powered down. For use in clock distribution mode. | R10 | 19 | |
OSCout_DIV | 0 | Divide-by-8 | OSCout divider value | R10 | 18:16 [3] | |
Mode | VCO_MUX | 0 | VCO | Select VCO or VCO Divider output | R10 | 12 |
EN_FEEDBACK_MUX | 0 | Disabled | Feedback MUX is powered down. | R10 | 11 | |
VCO_DIV | 2 | Divide-by-2 | VCO Divide value | R10 | 10:8 [3] | |
FEEDBACK_MUX | 0 | CLKout0 | Selects CLKout to feedback into the PLL1 N divider | R10 | 7:5 [3] | |
MODE | 0 | Internal VCO | Device mode | R11 | 31:27 [5] | |
Clock Synchronization | EN_SYNC | 1 | Enabled | Enables synchronization circuitry. | R11 | 26 |
NO_SYNC_CLKout5 | 0 | Will sync | Disable individual clock groups from becoming synchronized. | R11 | 25 | |
NO_SYNC_CLKout4 | 1 | Will not sync | R11 | 24 | ||
NO_SYNC_CLKout3 | 1 | Will not sync | R11 | 23 | ||
NO_SYNC_CLKout2 | 0 | Will sync | R11 | 22 | ||
NO_SYNC_CLKout1 | 0 | Will sync | R11 | 21 | ||
NO_SYNC_CLKout0 | 0 | Will sync | R11 | 20 | ||
SYNC_MUX | 0 | Logic Low | Mux controlling SYNC pin when set to output | R11 | 19:18 [2] | |
SYNC_QUAL | 0 | Not qualified | Allows SYNC operations to be qualified by a clock output. | R11 | 17 | |
SYNC_POL_INV | 1 | Logic Low | Sets the polarity of the SYNC pin when input | R11 | 16 | |
SYNC_EN_AUTO | 0 | Manual | SYNC is not started by programming a register R0 to R5. | R11 | 15 | |
SYNC_TYPE | 1 | Input w/ Pull-up |
SYNC IO pin type | R11 | 14:12 [3] | |
Other Mode Control | EN_PLL2_XTAL | 0 | Disabled | Enable Crystal oscillator for OSCin | R11 | 5 |
LD_MUX | 3 | PLL1 and 2 DLD | Lock detect mux selection when output | R12 | 31:27 [5] | |
LD_TYPE | 3 | Output (Push-Pull) |
LD IO pin type | R12 | 26:24 [3] | |
SYNC_PLL2_DLD | 0 | Normal | Force synchronization mode until PLL2 locks | R12 | 23 | |
SYNC_PLL1_DLD | 0 | Normal | Force synchronization mode until PLL1 locks | R12 | 22 | |
EN_TRACK | 1 | Enable Tracking | DAC tracking of the PLL1 tuning voltage | R12 | 8 | |
HOLDOVER_MODE | 2 | Enable Holdover | Causes holdover to activate when lock is lost | R12 | 7:6 [2] | |
HOLDOVER_MUX | 7 | uWire Readback | Holdover mux selection | R13 | 31:27 [5] | |
HOLDOVER_TYPE | 3 | Output (Push-Pull) |
HOLDOVER IO pin type | R13 | 26:24 [3] | |
Status_CLKin1_MUX | 0 | Logic Low | Status_CLKin1 pin MUX selection | R13 | 22:20 [3] | |
Status_CLKin0_TYPE | 2 | Input w/ Pull-down | Status_CLKin0 IO pin type | R13 | 18:16 [3] | |
DISABLE_DLD1_DET | 0 | Not Disabled | Disables PLL1 DLD falling edge from causing HOLDOVER mode to be entered | R13 | 15 | |
Status_CLKin0_MUX | 0 | Logic Low | Status_CLKin0 pin MUX selection | R13 | 14:12 [3] | |
CLKin_SELECT_MODE | 3 | Manual Select | Mode to use in determining reference CLKin for PLL1 | R13 | 11:9 [3] | |
CLKin_Sel_INV | 0 | Active High | Invert Status 0 and 1 pin polarity for input(2) | R13 | 8 | |
CLKin Control | EN_CLKin1 | 1 | Usable | Set CLKin1 to be usable | R13 | 6 |
EN_CLKin0 | 1 | Usable | Set CLKin0 to be usable | R13 | 5 | |
LOS_TIMEOUT | 0 | 1200 ns, 420 kHz | Time until no activity on CLKin asserts LOS | R14 | 31:30 [2] | |
EN_LOS | 1 | Enabled | Loss of Signal Detect at CLKin | R14 | 28 | |
Status_CLKin1_TYPE | 2 | Input w/ Pull-down | Status_CLKin1 pin IO pin type | R14 | 26:24 [3] | |
CLKin1_BUF_TYPE | 0 | Bipolar | CLKin1 Buffer Type | R14 | 21 | |
CLKin0_BUF_TYPE | 0 | Bipolar | CLKin0 Buffer Type | R14 | 20 | |
DAC Control | DAC_HIGH_TRIP | 0 | ~50 mV from Vcc | Voltage from Vcc at which holdover mode is entered if EN_VTUNE_RAIL_DAC is enabled. | R14 | 19:14 [6] |
DAC_LOW_TRIP | 0 | ~50 mV from GND | Voltage from GND at which holdover mode is entered if EN_VTUNE_RAIL_DAC is enabled. | R14 | 11:6 [6] | |
EN_VTUNE_RAIL_DET | 0 | Disabled | Enable PLL1 unlock state when DAC trip points are achieved | R14 | 5 | |
MAN_DAC | 512 | 3 V / 2 | Writing to this register will set the value for DAC when in manual override. Readback from this register is DAC value. |
R15 | 31:22 [10] | |
EN_MAN_DAC | 0 | Disabled | Set manual DAC override | R15 | 20 | |
HOLDOVER_DLD_CNT | 512 | 512 counts | Lock must be valid n many clocks of PLL1 PDF before holdover mode is exited. | R15 | 19:6 [14] | |
FORCE_HOLDOVER | 0 | Holdover not forced | Forces holdover mode. | R15 | 5 | |
XTAL_LVL | 0 | 1.65 Vpp | Sets drive power level of Crystal | R16 | 31:30 [2] | |
PLL Control | PLL2_C4_LF | 0 | 10 pF | PLL2 integrated capacitor C4 value | R24 | 31:28 [4] |
PLL2_C3_LF | 0 | 10 pF | PLL2 integrated capacitor C3 value | R24 | 27:24 [4] | |
PLL2_R4_LF | 0 | 200 Ω | PLL2 integrated resistor R4 value | R24 | 22:20 [3] | |
PLL2_R3_LF | 0 | 200 Ω | PLL2 integrated resistor R3 value | R24 | 18:16 [3] | |
PLL1_N_DLY | 0 | No delay | Delay in PLL1 feedback path to decrease lag from input to output | R24 | 14:12 [3] | |
PLL1_R_DLY | 0 | No delay | Delay in PLL1 reference path to increase lag from input to output | R24 | 10:8 [3] | |
PLL1_WND_SIZE | 3 | 40 ns | Window size used for digital lock detect for PLL1 | R24 | 7:6 [2] | |
DAC_CLK_DIV | 4 | Divide-by-4 | DAC update clock divisor. Divides PLL1 phase detector frequency. | R25 | 31:22 [10] | |
PLL1_DLD_CNT | 1024 | 1024 cycles | Lock must be valid n many cycles before LD is asserted | R25 | 19:6 [14] | |
PLL2_WND_SIZE | 0 | Reserved (1) |
Window size used for digital lock detect for PLL2 | R26 | 31:30 [2] | |
EN_PLL2_REF_2X | 0 | Disabled, 1x | Doubles reference frequency of PLL2. | R26 | 29 | |
PLL2_CP_POL | 0 | Negative | Polarity of PLL2 Charge Pump | R26 | 28 | |
PLL2_CP_GAIN | 3 | 3.2 mA | PLL2 Charge Pump Gain | R26 | 27:26 [2] | |
PLL2_DLD_CNT | 8192 | 8192 Counts | Number of PDF cycles which phase error must be within DLD window before LD state is asserted. | R26 | 19:6 [14] | |
PLL2_CP_TRI | 0 | Active | PLL2 Charge Pump Active | R26 | 5 | |
PLL1_CP_POL | 1 | Positive | Polarity of PLL1 Charge Pump | R27 | 28 | |
PLL1_CP_GAIN | 0 | 100 uA | PLL1 Charge Pump Gain | R27 | 27:26 [2] | |
CLKin1_PreR_DIV | 0 | Divide-by-1 | CLKin1 Pre-R divide value (1, 2, 4, or 8) | R27 | 23:22 [2] | |
CLKin0_PreR_DIV | 0 | Divide-by-1 | CLKin0 Pre-R divide value (1, 2, 4, or 8) | R27 | 21:20 [2] | |
PLL1_R | 96 | Divide-by-96 | PLL1 R Divider (1 to 16383) | R27 | 19:6 [14] | |
PLL1_CP_TRI | 0 | Active | PLL1 Charge Pump Active | R27 | 5 | |
PLL2_R | 4 | Divide-by-4 | PLL2 R Divider (1 to 4095) | R28 | 31:20 [12] | |
PLL1_N | 192 | Divide-by-192 | PLL1 N Divider (1 to 16383) | R28 | 19:6 [14] | |
OSCin_FREQ | 7 | 448 to 511 MHz | OSCin frequency range | R29 | 26:24 [3] | |
PLL2_FAST_PDF | 1 | PLL2 PDF > 100 MHz | When set, PLL2 PDF of greater than 100 MHz may be used | R29 | 23 | |
PLL2_N_CAL | 48 | Divide-by-48 | Actual PLL2 N divider value used in calibration routine. | R29 | 22:5 [18] | |
PLL2_P | 2 | Divide-by-2 | PLL2 N Divider Prescaler (2 to 8) | R30 | 26:24 [3] | |
PLL2_N | 48 | Divide-by-48 | PLL2 N Divider (1 to 262143) | R30 | 22:5 [18] | |
READBACK_LE | 0 | LEuWire Low for Readback | State LEuWire pin must be in for readback | R31 | 21 | |
READBACK_ADDR | 31 | Register 31 | Register to read back | R31 | 20:16 [5] | |
uWire_LOCK | 0 | Writable | The values of registers R0 to R30 are lockable | R31 | 5 |
Registers R0 through R5 control the 12 clock outputs CLKout0 to CLKout5. Register R0 controls CLKout0 and CLKout1, Register R1 controls CLKout2 and so on. All functions of the bits in these six registers are identical except the different registers control different clock outputs.
The RESET bit is only in register R0.
The POWERDOWN bit is only in register R1.
The CLKoutX_OSCin_Sel bit is only in registers R3 and R4.
This bit powers down the clock as specified by CLKoutX. This includes the divider, digital delay, analog delay, and output buffers.
R0 to R5[31] | STATE |
---|---|
0 | Power up clock group |
1 | Power down clock group |
This bit sets the source for the clock output CLKoutX. The selected source will be either from a VCO via Mode Mux1 or from the OSCin buffer.
This bit is valid only for registers R3 and R4, clock groups CLKout3 and CLKout4 respectively. All other clock output groups are driven by a VCO via Mode Mux1.
R3 to R4[30] | CLOCK GROUP SOURCE |
---|---|
0 | VCO |
1 | OSCin |
These bits individually select the analog delay block (CLKoutX_ADLY) for use with CLKoutX. Analog delay is powered down when not selected. Analog delay may not operate at frequencies above the minimum-ensured maximum output frequency of 1536 MHz.
R0 to R5[28:29] | DEFINITION |
---|---|
0 (0x00) | Analog delay powered down |
1 (0x01) | Reserved |
2 (0x02) | Reserved |
3 (0x03) | Analog delay selected |
CLKoutX_DDLY and CLKoutX_HS set the digital delay used for CLKoutX and CLKoutY. This value only takes effect during a SYNC event and if the NO_SYNC_CLKoutX bit is cleared for this clock group. See Clock Output Synchronization (SYNC).
Programming CLKoutX_DDLY can require special attention. See Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY for more details.
Using a CLKoutX_DDLY value of 13 or greater will cause the clock group to operate in extended mode regardless of the clock group's divide value or the half step value.
One clock cycle is equal to the period of the clock distribution path. The period of the clock distribution path is equal to VCO Divider value divided by the frequency of the VCO. If the VCO divider is disabled or an external VCO is used, the VCO divide value is treated as 1.
tclock distribution path = VCO divide value / fVCO
R0 to R5[27:18] | DELAY | POWER MODE |
---|---|---|
0 (0x00) | 5 clock cycles | Normal Mode |
1 (0x01) | 5 clock cycles | |
2 (0x02) | 5 clock cycles | |
3 (0x03) | 5 clock cycles | |
4 (0x04) | 5 clock cycles | |
5 (0x05) | 5 clock cycles | |
6 (0x06) | 6 clock cycles | |
7 (0x07) | 7 clock cycles | |
... | ... | |
12 (0x0C) | 12 clock cycles | |
13 (0x0D) | 13 clock cycles | Extended Mode |
... | ... | |
520 (0x208) | 520 clock cycles | |
521 (0x209) | 521 clock cycles | |
522 (0x20A) | 522 clock cycles |
The RESET bit is located in register R0 only. Setting this bit will cause the silicon default values to be loaded. When programming register R0 with the RESET bit set, all other programmed values are ignored. After resetting the device, the register R0 must be programmed again (with RESET = 0) to set non-default values in register R0.
The reset occurs on the falling edge of the LEuWire pin which loaded R0 with RESET = 1.
The RESET bit is automatically cleared upon writing any other register. For instance, when R0 is written to again with default values.
R0[17] | STATE |
---|---|
0 | Normal operation |
1 | Reset (automatically cleared) |
The POWERDOWN bit is located in register R1 only. Setting the bit causes the device to enter powerdown mode. Normal operation is resumed by clearing this bit via MICROWIRE.
R1[17] | STATE |
---|---|
0 | Normal operation |
1 | Powerdown |
This bit subtracts a half clock cycle of the clock distribution path period to the digital delay of CLKoutX and CLKoutY. CLKoutX_HS is used together with CLKoutX_DDLY to set the digital delay value.
When changing CLKoutX_HS, the digital delay immediately takes effect without a SYNC event.
R0 to R5[16] | STATE |
---|---|
0 | Normal |
1 | Subtract half of a clock distribution path period from the total digital delay |
CLKoutX_DIV sets the divide value for the clock group. The divide may be even or odd. Both even and odd divides output a 50% duty cycle clock.
Using a divide value of 26 or greater will cause the clock group to operate in extended mode regardless of the clock group's digital delay value.
Programming CLKoutX_DIV can require special attention. See section Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY for more details.
R0 to R5[15:5] | DIVIDE VALUE | POWER MODE |
---|---|---|
0 (0x00) | Reserved | Normal Mode |
1 (0x01) | 1 (1) | |
2 (0x02) | 2 (2) | |
3 (0x03) | 3 | |
4 (0x04) | 4 (2) | |
5 (0x05) | 5 (2) | |
6 (0x06) | 6 | |
... | ... | |
24 (0x18) | 24 | |
25 (0x19) | 25 | |
26 (0x1A) | 26 | Extended Mode |
27 (0x1B) | 27 | |
... | ... | |
1044 (0x414) | 1044 | |
1045 (0x415) | 1045 |
Registers R6 to R8 set the clock output types and analog delays.
The clock output types of the LMK04208 are individually programmable. The CLKoutX_TYPE registers set the output type of an individual clock output to LVDS, LVPECL, LVCMOS, or powers down the output buffer. Note that LVPECL supports four different amplitude levels and LVCMOS supports single LVCMOS outputs, inverted, and normal polarity of each output pin for maximum flexibility.
Table 26 shows at what register and address the specified clock output CLKoutX_TYPE register is located.
The CLKoutX_TYPE table shows the programming definition for these registers.
CLKoutX | PROGRAMMING ADDRESS |
---|---|
CLKout0 | R6[23:20] |
CLKout1 | R6[27:24] |
CLKout2 | R7[23:20] |
CLKout3 | R7[27:24] |
CLKout4 | R8[19:16] |
CLKout5 | R8[27:24] |
R6-R8[27:24, 23:20] | DEFINITION |
---|---|
0 (0x00) | Power down |
1 (0x01) | LVDS |
2 (0x02) | LVPECL (700 mVpp) |
3 (0x03) | LVPECL (1200 mVpp) |
4 (0x04) | LVPECL (1600 mVpp) |
5 (0x05) | LVPECL (2000 mVpp) |
6 (0x06) | LVCMOS (Norm/Inv) |
7 (0x07) | LVCMOS (Inv/Norm) |
8 (0x08) | LVCMOS (Norm/Norm) |
9 (0x09) | LVCMOS (Inv/Inv)(1) |
10 (0x0A) | LVCMOS (Low/Norm)(1) |
11 (0x0A) | LVCMOS (Low/Inv)(1) |
12 (0x0C) | LVCMOS (Norm/Low)(1) |
13 (0x0D) | LVCMOS (Inv/Low)(1) |
14 (0x0E) | LVCMOS (Low/Low)(1) |
These registers control the analog delay of the clock group CLKoutX. Adding analog delay to the output will increase the noise floor of the output. For this analog delay to be active for a clock output, it must be selected with CLKoutX_ADLY_SEL. If neither clock output in a clock group selects the analog delay, then the analog delay block is powered down. Analog delay may not operate at frequencies above the minimum-ensured maximum output frequency of 1536 MHz.
In addition to the programmed delay, a fixed 500 ps of delay will be added by engaging the delay block.
The programming addresses table shows at what register and address the specified clock output CLKoutX_ADLY register is located.
The CLKoutX_ADLY table shows the programming definition for these registers.
CLKoutX_ADLY | PROGRAMMING ADDRESS |
---|---|
CLKout0_ADLY | R6[9:5] |
CLKout1_ADLY | R6[15:11] |
CLKout2_ADLY | R7[9:5] |
CLKout3_ADLY | R7[15:11] |
CLKout4_ADLY | R8[9:5] |
CLKout5_ADLY | R8[15:11] |
R6-R8[15:11, 9:5] | DEFINITION |
---|---|
0 (0x00) | 500 ps + No delay |
1 (0x01) | 500 ps + 25 ps |
2 (0x02) | 500 ps + 50 ps |
3 (0x03) | 500 ps + 75 ps |
4 (0x04) | 500 ps + 100 ps |
5 (0x05) | 500 ps + 125 ps |
6 (0x06) | 500 ps + 150 ps |
7 (0x07) | 500 ps + 175 ps |
8 (0x08) | 500 ps + 200 ps |
9 (0x09) | 500 ps + 225 ps |
10 (0x0A) | 500 ps + 250 ps |
11 (0x0B) | 500 ps + 275 ps |
12 (0x0C) | 500 ps + 300 ps |
13 (0x0D) | 500 ps + 325 ps |
14 (0x0E) | 500 ps + 350 ps |
15 (0x0F) | 500 ps + 375 ps |
16 (0x10) | 500 ps + 400 ps |
17 (0x11) | 500 ps + 425 ps |
18 (0x12) | 500 ps + 450 ps |
19 (0x13) | 500 ps + 475 ps |
20 (0x14) | 500 ps + 500 ps |
21 (0x15) | 500 ps + 525 ps |
22 (0x16) | 500 ps + 550 ps |
23 (0x17) | 500 ps + 575 ps |
The OSCout clock output has a programmable output type. The OSCout_TYPE register sets the output type to LVDS, LVPECL, LVCMOS, or powers down the output buffer. Note that LVPECL supports four different amplitude levels and LVCMOS supports dual and single LVCMOS outputs with inverted, and normal polarity of each output pin for maximum flexibility.
To turn on the output, the OSCout_TYPE must be set to a non-power down setting and enabled with EN_OSCout, OSCout Output Enable.
R10[27:24] | DEFINITION |
---|---|
0 (0x00) | Powerdown |
1 (0x01) | LVDS |
2 (0x02) | LVPECL (700 mVpp) |
3 (0x03) | LVPECL (1200 mVpp) |
4 (0x04) | LVPECL (1600 mVpp) |
5 (0x05) | LVPECL (2000 mVpp) |
6 (0x06) | LVCMOS (Norm/Inv) |
7 (0x07) | LVCMOS (Inv/Norm) |
8 (0x08) | LVCMOS (Norm/Norm)(1) |
9 (0x09) | LVCMOS (Inv/Inv)(1) |
10 (0x0A) | LVCMOS (Low/Norm)(1) |
11 (0x0B) | LVCMOS (Low/Inv)(1) |
12 (0x0C) | LVCMOS (Norm/Low)(1) |
13 (0x0D) | LVCMOS (Inv/Low)(1) |
14 (0x0E) | LVCMOS (Low/Low)(1) |
EN_OSCout is used to enable an oscillator buffered output.
R10[22] | OUTPUT STATE |
---|---|
0 | OSCout Disabled |
1 | OSCout Enabled |
Note: In addition to enabling the output with EN_OSCout. The OSCout_TYPE must be programmed to a non-power down value for the output buffer to power up.
Sets OSCout buffer to output a divided or bypassed OSCin signal. The divisor is set by OSCout_DIV, Oscillator Output Divide.
R10[20] | MUX OUTPUT |
---|---|
0 | Bypass divider |
1 | Divided |
Except in clock distribution mode, the OSCin buffer must always be powered up.
In clock distribution mode, the OSCin buffer must be powered down if not used.
R10[19] | OSCin BUFFER |
---|---|
0 | Normal Operation |
1 | Powerdown |
The OSCout divider can be programmed from 2 to 8. Divide by 1 is achieved by bypassing the divider with OSCout_MUX, Clock Output Mux.
Note that OSCout_DIV will be in the PLL1 N feedback path if OSCout_MUX selects divided as an output. When OSCout_DIV is in the PLL1 N feedback path, the OSCout_DIV divide value must be accounted for when programming PLL1 N.
See PLL Programming for more information on programming PLL1 to lock.
R10[18:16] | DIVIDE |
---|---|
0 (0x00) | 8 |
1 (0x01) | 2 |
2 (0x02) | 2 |
3 (0x03) | 3 |
4 (0x04) | 4 |
5 (0x05) | 5 |
6 (0x06) | 6 |
7 (0x07) | 7 |
When the internal VCO is used, the VCO divider can be selected to divide the VCO output frequency to reduce the frequency on the clock distribution path. TI recommends using the VCO directly unless:
A consequence of using the VCO divider is a small degradation in phase noise.
R10[12] | DEFINITION |
---|---|
0 | VCO selected |
1 | VCO divider selected |
When using 0-delay or dynamic digital delay (SYNC_QUAL = 1), EN_FEEDBACK_MUX must be set to 1 to power up the feedback mux.
R10[11] | DEFINITION |
---|---|
0 | Feedback mux powered down |
1 | Feedback mux enabled |
Divide value of the VCO Divider.
See PLL Programming for more information on programming PLL2 to lock.
R10[10:8] | DIVIDE |
---|---|
0 (0x00) | 8 |
1 (0x01) | 2 |
2 (0x02) | 2 |
3 (0x03) | 3 |
4 (0x04) | 4 |
5 (0x05) | 5 |
6 (0x06) | 6 |
7 (0x07) | 7 |
When in 0-delay mode, the feedback mux selects the clock output to be fed back into the PLL1 N Divider.
R10[7:5] | MUX OUTPUT |
---|---|
0 (0x00) | CLKout0 |
1 (0x01) | CLKout1 |
2 (0x02) | CLKout2 |
3 (0x03) | CLKout3 |
4 (0x04) | CLKout4 |
5 (0x05) | CLKout5 |
6 (0x06) | FBCLKin/FBCLKin* |
MODE determines how the LMK04208 operates from a high level. Different blocks of the device can be powered up and down for specific application requirements from a dual loop architecture to clock distribution.
The LMK04208 can operate in:
For the PLL modes, deterministic phase delay with respect to the input can be achieved with the 0-delay mode.
For the PLL modes it is also possible to use an external VCO.
R11[31:27] | VALUE |
---|---|
0 (0x00) | Dual PLL, Internal VCO |
1 (0x01) | Reserved |
2 (0x02) | Dual PLL, Internal VCO, 0-Delay |
3 (0x03) | Dual PLL, External VCO (Fin) |
4 (0x04) | Reserved |
5 (0x05) | Dual PLL, External VCO (Fin), 0-Delay |
6 (0x06) | PLL2, Internal VCO |
7 (0x07) | Reserved |
8 (0x08) | PLL2, Internal VCO, 0–Delay |
9 (0x09) | Reserved |
10 (0x0A) | Reserved |
11 (0x0B) | PLL2, External VCO (Fin) |
12 (0x0C) | Reserved |
13 (0x0D) | Reserved |
14 (0x0E) | Reserved |
15 (0x0F) | Reserved |
16 (0x10) | Clock Distribution |
The EN_SYNC bit (default on) must be enabled for synchronization to work. Synchronization is required for dynamic digital delay.
The synchronization enable may be turned off once the clocks are operating to save current. If EN_SYNC is set after it has been cleared (a transition from 0 to 1), a SYNC is generated that can disrupt the active clock outputs. Setting the NO_SYNC_CLKoutX bits will prevent this SYNC pulse from affecting the output clocks. Setting the EN_SYNC bit is not a valid method for synchronizing the clock outputs. See the Clock Output Synchronization section for more information on synchronization.
R11[26] | DEFINITION |
---|---|
0 | Synchronization disabled |
1 | Synchronization enabled |
The NO_SYNC_CLKoutX bits prevent individual clock groups from becoming synchronized during a SYNC event. A reason to prevent individual clock groups from becoming synchronized is that during synchronization, the clock output is in a fixed low state or can have a glitch pulse.
By disabling SYNC on a clock group, it will continue to operate normally during a SYNC event.
Digital delay requires a SYNC operation to take effect. If NO_SYNC_CLKoutX is set before a SYNC event, the digital delay value will be unused.
Setting the NO_SYNC_CLKoutX bit has no effect on clocks already synchronized together.
NO_SYNC_CLKoutX | PROGRAMMING ADDRESS |
---|---|
CLKout0 | R11:20 |
CLKout1 | R11:21 |
CLKout2 | R11:22 |
CLKout3 | R11:23 |
CLKout4 | R11:24 |
CLKout5 | R11:25 |
R11[25, 24, 23, 22, 21, 20] | DEFINITION |
---|---|
0 | CLKoutX will synchronize |
1 | CLKoutX will not synchronize |
Mux controlling SYNC pin when type is an output.
All the outputs logic is active high when SYNC_TYPE = 3 (Output). All the outputs logic is active low when SYNC_TYPE = 4 (Output Inverted). For example, when SYNC_MUX = 0 (Logic Low) and SYNC_TYPE = 3 (Output) then SYNC outputs a logic low. When SYNC_MUX = 0 (Logic Low) and SYNC_TYPE = 4 (Output Inverted) then SYNC outputs a logic high.
R11[19:18] | SYNC PIN OUTPUT |
---|---|
0 (0x00) | Logic Low |
1 (0x01) | Reserved |
2 (0x02) | Reserved |
3 (0x03) | uWire Readback |
When SYNC_QUAL is set, clock outputs will be synchronized to an existing clock output selected by FEEDBACK_MUX. By using the NO_SYNC_CLKoutX bits, selected clock outputs will not be interrupted during the SYNC event.
Qualifying the SYNC by an output clock means that the pulse which turns the clock outputs off and on will have a fixed time relationship to the qualifying output clock.
SYNC_QUAL = 1 requires CLKout2_PD = 0 for proper operation. CLKout2_TYPE may be set to Powerdown mode.
See Clock Output Synchronization (SYNC) for more information.
R11[17] | MODE |
---|---|
0 | No qualification |
1 | Qualification by clock output from feedback mux (Must set CLKout2_PD = 0) |
Sets the polarity of the SYNC pin when input. When SYNC is asserted the clock outputs will transition to a low state.
See Clock Output Synchronization (SYNC) for more information on SYNC. A SYNC event can be generated by toggling this bit through the MICROWIRE interface.
R11[16] | POLARITY |
---|---|
0 | SYNC is active high |
1 | SYNC is active low |
When set, causes a SYNC event to occur when programming register R0 to R5 to adjust digital delay values.
The SYNC event will coincide with the LEuWire pin falling edge.
Refer to Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY for more information on possible special programming considerations when SYNC_EN_AUTO = 1.
R11[15] | MODE |
---|---|
0 | Manual SYNC |
1 | SYNC Internally Generated |
Sets the IO type of the SYNC pin.
R11[14:12] | POLARITY |
---|---|
0 (0x00) | Input |
1 (0x01) | Input w/ pull-up resistor |
2 (0x02) | Input w/ pull-down resistor |
3 (0x03) | Output (push-pull) |
4 (0x04) | Output inverted (push-pull) |
5 (0x05) | Output (open source) |
6 (0x06) | Output (open drain) |
When in output mode, the SYNC input is forced to 0 regardless of the SYNC_MUX setting. A synchronization can then be activated by uWire by programming the SYNC_POL_INV register to active low to assert SYNC. SYNC can then be released by programming SYNC_POL_INV to active high. Using this uWire programming method to create a SYNC event saves the need for an IO pin from another device.
If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be enabled with this bit in order to complete the oscillator circuit.
R11[5] | OSCILLATOR AMPLIFIER STATE |
---|---|
0 | Disabled |
1 | Enabled |
LD_MUX sets the output value of the LD pin.
All the outputs logic is active high when LD_TYPE = 3 (Output). All the outputs logic is active low when LD_TYPE = 4 (Output Inverted). For example, when LD_MUX = 0 (Logic Low) and LD_TYPE = 3 (Output) then Status_LD outputs a logic low. When LD_MUX = 0 (Logic Low) and LD_TYPE = 4 (Output Inverted) then Status_LD outputs a logic high.
R12[31:27] | MODE |
---|---|
0 (0x00) | Logic Low |
1 (0x01) | PLL1 DLD |
2 (0x02) | PLL2 DLD |
3 (0x03) | PLL1 and PLL2 DLD |
4 (0x04) | Holdover Status |
5 (0x05) | DAC Locked |
6 (0x06) | Reserved |
7 (0x07) | uWire Readback |
8 (0x08) | DAC Rail |
9 (0x09) | DAC Low |
10 (0x0A) | DAC High |
11 (0x0B) | PLL1_N |
12 (0x0C) | PLL1_N/2 |
13 (0x0D) | PLL2 N |
14 (0x0E) | PLL2 N/2 |
15 (0x0F) | PLL1_R |
16 (0x10) | PLL1_R/2 |
17 (0x11) | PLL2 R (1) |
18 (0x12) | PLL2 R/2 (1) |
Sets the IO type of the LD pin.
R12[26:24] | POLARITY |
---|---|
0 (0x00) | Reserved |
1 (0x01) | Reserved |
2 (0x02) | Reserved |
3 (0x03) | Output (push-pull) |
4 (0x04) | Output inverted (push-pull) |
5 (0x05) | Output (open source) |
6 (0x06) | Output (open drain) |
By setting SYNC_PLLX_DLD a SYNC mode will be engaged (asserted SYNC) until PLL1 and/or PLL2 locks.
SYNC_QUAL must be 0 to use this functionality.
R12[23] | SYNC MODE FORCED |
---|---|
0 | No |
1 | Yes |
R12[22] | SYNC MODE FORCED |
---|---|
0 | No |
1 | Yes |
Enable the DAC to track the PLL1 tuning voltage. For optional use in in holdover mode.
Tracking can be used to monitor PLL1 voltage by readback of DAC_CNT register in any mode.
R12[8] | DAC TRACKING |
---|---|
0 | Disabled |
1 | Enabled |
Enable the holdover mode.
R12[7:6] | HOLDOVER MODE |
---|---|
0 | Reserved |
1 | Disabled |
2 | Enabled |
3 | Reserved |
HOLDOVER_MUX sets the output value of the Status_Holdover pin.
The outputs are active high when HOLDOVER_TYPE = 3 (Output). The outputs are active low when HOLDOVER_TYPE = 4 (Output Inverted).
R13[31:27] | DEFINITION |
---|---|
0 (0x00) | Logic Low |
1 (0x01) | PLL1 DLD |
2 (0x02) | PLL2 DLD |
3 (0x03) | PLL1 and PLL2 DLD |
4 (0x04) | Holdover Status |
5 (0x05) | DAC Locked |
6 (0x06) | Reserved |
7 (0x07) | uWire Readback |
8 (0x08) | DAC Rail |
9 (0x09) | DAC Low |
10 (0x0A) | DAC High |
11 (0x0B) | PLL1 N |
12 (0x0C) | PLL1 N/2 |
13 (0x0D) | PLL2 N |
14 (0x0E) | PLL2 N/2 |
15 (0x0F) | PLL1 R |
16 (0x10) | PLL1 R/2 |
17 (0x11) | PLL2 R (1) |
18 (0x12) | PLL2 R/2 (1) |
Sets the IO mode of the Status_Holdover pin.
R13[26:24] | POLARITY |
---|---|
0 (0x00) | Reserved |
1 (0x01) | Reserved |
2 (0x02) | Reserved |
3 (0x03) | Output (push-pull) |
4 (0x04) | Output inverted (push-pull) |
5 (0x05) | Output (open source) |
6 (0x06) | Output (open drain) |
Status_CLKin1_MUX sets the output value of the Status_CLKin1 pin. If Status_CLKin1_TYPE is set to an input type, this register has no effect. This MUX register only sets the output signal.
The outputs are active high when Status_CLKin1_TYPE = 3 (Output). The outputs are active low when Status_CLKin1_TYPE = 4 (Output Inverted).
R13[22:20] | DEFINITION |
---|---|
0 (0x00) | Logic Low |
1 (0x01) | CLKin1 LOS |
2 (0x02) | CLKin1 Selected |
3 (0x03) | DAC Locked |
4 (0x04) | DAC Low |
5 (0x05) | DAC High |
6 (0x06) | uWire Readback |
Status_CLKin0_TYPE sets the IO type of the Status_CLKin0 pin.
R13[18:16] | DEFINITION |
---|---|
0 (0x00) | Input |
1 (0x01) | Input w/ pull-up resistor |
2 (0x02) | Input w/ pull-down resistor |
3 (0x03) | Output (push-pull) |
4 (0x04) | Output inverted (push-pull) |
5 (0x05) | Output (open source) |
6 (0x06) | Output (open drain) |
DISABLE_DLD1_DET disables the HOLDOVER mode from being activated when PLL1 lock detect signal transitions from high to low.
When using Pin Select Mode as the input clock switch mode, this bit should normally be set.
R13[15] | HOLDOVER DLD1 DETECT |
---|---|
0 | PLL1 DLD causes clock switch event |
1 | PLL1 DLD does not cause clock switch event |
CLKin0_MUX sets the output value of the Status_CLKin0 pin. If Status_CLKin0_TYPE is set to an input type, this register has no effect. This MUX register only sets the output signal.
The outputs logic is active high when Status_CLKin0_TYPE = 3 (Output). The outputs logic is active low when Status_CLKin0_TYPE = 4 (Output Inverted).
R13[14:12] | DEFINITION |
---|---|
0 (0x00) | Logic Low |
1 (0x01) | CLKin0 LOS |
2 (0x02) | CLKin0 Selected |
3 (0x03) | DAC Locked |
4 (0x04) | DAC Low |
5 (0x05) | DAC High |
6 (0x06) | uWire Readback |
CLKin_SELECT_MODE sets the mode used in determining reference CLKin for PLL1.
R13[11:9] | MODE |
---|---|
0 (0x00) | CLKin0 Manual |
1 (0x01) | CLKin1 Manual |
2 (0x02) | Reserved |
3 (0x03) | Pin Select Mode |
4 (0x04) | Auto Mode |
5 (0x05) | Reserved |
6 (0x06) | Auto mode and next clock pin select |
7 (0x07) | Reserved |
CLKin_Sel_INV sets the input polarity of Status_CLKin0 and Status_CLKin1 pins.
Inversion for Status 0 and 1 pins is only valid for CLKin_SELECT_MODE = 0x06.
R13[8] | INPUT |
---|---|
0 | Active High |
1 | Active Low |
Each clock input can individually be enabled to be used during auto-switching CLKin_SELECT_MODE. Clock input switching priority is always CLKin0 → CLKin1.
R13[6] | ENABLED |
---|---|
0 | No |
1 | Yes |
R13[5] | ENABLED |
---|---|
0 | No |
1 | Yes |
This bit controls the amount of time in which no activity on a CLKin causes LOS (Loss-of-Signal) to be asserted.
R14[31:30] | TIMEOUT |
---|---|
0 (0x00) | 1200 ns, 420 kHz |
1 (0x01) | 206 ns, 2.5 MHz |
2 (0x02) | 52.9 ns, 10 MHz |
3 (0x03) | 23.7 ns, 22 MHz |
Enables the LOS (Loss-of-Signal) timeout control.
R14[28] | LOS |
---|---|
0 | Disabled |
1 | Enabled |
Sets the IO type of the Status_CLKin1 pin.
R14[26:24] | POLARITY |
---|---|
0 (0x00) | Input |
1 (0x01) | Input w/ pull-up resistor |
2 (0x02) | Input w/ pull-down resistor |
3 (0x03) | Output (push-pull) |
4 (0x04) | Output inverted (push-pull) |
5 (0x05) | Output (open source) |
6 (0x06) | Output (open drain) |
There are two input buffer types for the PLL1 reference clock inputs: either bipolar or CMOS. Bipolar is recommended for differential inputs such as LVDS and LVPECL. CMOS is recommended for DC coupled single ended inputs.
When using bipolar, CLKinX and CLKinX* input pins must be AC coupled when using a differential or single ended input.
When using CMOS, CLKinX and CLKinX* input pins may be AC or DC coupled with a differential input.
When using CMOS in single ended mode, the unused clock input pin (CLKinX or CLKinX*) must be AC grounded. The used clock input pin (CLKinX* or CLKinX) may be AC or DC coupled to the signal source.
The programming addresses table shows at what register and address the specified CLKinX_BUF_TYPE bit is located.
The CLKinX_BUF_TYPE table shows the programming definition for these registers.
CLKinX_BUF_TYPE | PROGRAMMING ADDRESS |
---|---|
CLKin1_BUF_TYPE | R14[21] |
CLKin0_BUF_TYPE | R14[20] |
R14[21, 20] | CLKinX BUFFER TYPE |
---|---|
0 | Bipolar |
1 | CMOS |
Voltage from Vcc at which holdover mode is entered if EN_VTUNE_RAIL_DAC is enabled. This will also set flags which can be monitored out Status_LD/Status_Holdover pins.
Step size is ~51 mV.
R14[19:14] | TRIP VOLTAGE FROM VCC (V) |
---|---|
0 (0x00) | 1 × Vcc / 64 |
1 (0x01) | 2 × Vcc / 64 |
2 (0x02) | 3 × Vcc / 64 |
3 (0x03) | 4 × Vcc / 64 |
4 (0x04) | 5 × Vcc / 64 |
... | ... |
61 (0x3D) | 62 × Vcc / 64 |
62 (0x3E) | 63 × Vcc / 64 |
63 (0x3F) | 64 × Vcc / 64 |
Voltage from GND at which holdover mode is entered if EN_VTUNE_RAIL_DAC is enabled. This will also set flags which can be monitored out Status_LD/Status_Holdover pins.
Step size is ~51 mV
R14[11:6] | TRIP VOLTAGE from GND (V) |
---|---|
0 (0x00) | 1 × Vcc / 64 |
1 (0x01) | 2 × Vcc / 64 |
2 (0x02) | 3 × Vcc / 64 |
3 (0x03) | 4 × Vcc / 64 |
4 (0x04) | 5 × Vcc / 64 |
... | ... |
61 (0x3D) | 62 × Vcc / 64 |
62 (0x3E) | 63 × Vcc / 64 |
63 (0x3F) | 64 × Vcc / 64 |
Enables the DAC Vtune rail detection. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated.
R14[5] | STATE |
---|---|
0 | Disabled |
1 | Enabled |
Sets the DAC value when in manual DAC mode in ~3.2 mV steps.
R15[31:22] | DAC VOLTAGE |
---|---|
0 (0x00) | 0 × Vcc / 1023 |
1 (0x01) | 1 × Vcc / 1023 |
2 (0x02) | 2 × Vcc / 1023 |
... | ... |
1023 (0x3FF) | 1023 × Vcc / 1023 |
This bit enables the manual DAC mode.
R15[20] | DAC MODE |
---|---|
0 | Automatic |
1 | Manual |
Lock must be valid for this many clocks of PLL1 PDF before holdover mode is exited.
R15[19:6] | EXIT COUNTS |
---|---|
0 (0x00) | Reserved |
1 (0x01) | 1 |
2 (0x02) | 2 |
... | ... |
16,383 (0x3FFF) | 16,383 |
This bit forces the holdover mode.
When holdover is forced, if in fixed CPout1 mode (EN_TRACK = 0 or 1, EN_MAN_DAC = 1) , then the DAC will set the programmed MAN_DAC value. If in tracked CPout1 mode (EN_TRACK = 1, EN_MAN_DAC = 0, EN_VTUNE_RAIL_DET = 0), then the DAC will set the current tracked DAC value.
Setting FORCE_HOLDOVER does not constitute a clock input switch event unless DISABLE_DLD1_DET = 0, since when in holdover mode, PLL1_DLD = 0 will trigger the clock input switch event.
R15[5] | HOLDOVER |
---|---|
0 | Disabled |
1 | Enabled |
Sets the peak amplitude on the tunable crystal.
Increasing this value can improve the crystal oscillator phase noise performance at the cost of increased current and higher crystal power dissipation levels.
R15[31:22] | PEAK AMPLITUDE(1) |
---|---|
0 (0x00) | 1.65 Vpp |
1 (0x01) | 1.75 Vpp |
2 (0x02) | 1.90 Vpp |
3 (0x03) | 2.05 Vpp |
This register must not be programmed, it is a readback only register.
The DAC_CNT register is 10 bits in size and located at readback bit position R23[23:14]. When using tracking mode for holdover, the DAC value can be readback at this address.
Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components.
Internal loop filter capacitor C4 can be set according to Table 78.
R24[31:28] | LOOP FILTER CAPACITANCE (pF) |
---|---|
0 (0x00) | 10 pF |
1 (0x01) | 15 pF |
2 (0x02) | 29 pF |
3 (0x03) | 34 pF |
4 (0x04) | 47 pF |
5 (0x05) | 52 pF |
6 (0x06) | 66 pF |
7 (0x07) | 71 pF |
8 (0x08) | 103 pF |
9 (0x09) | 108 pF |
10 (0x0A) | 122 pF |
11 (0x0B) | 126 pF |
12 (0x0C) | 141 pF |
13 (0x0D) | 146 pF |
14 (0x0E) | Reserved |
15 (0x0F) | Reserved |
Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components.
Internal loop filter capacitor C3 can be set according to Table 79.
R24[27:24] | LOOP FILTER CAPACITANCE (pF) |
---|---|
0 (0x00) | 10 pF |
1 (0x01) | 11 pF |
2 (0x02) | 15 pF |
3 (0x03) | 16 pF |
4 (0x04) | 19 pF |
5 (0x05) | 20 pF |
6 (0x06) | 24 pF |
7 (0x07) | 25 pF |
8 (0x08) | 29 pF |
9 (0x09) | 30 pF |
10 (0x0A) | 33 pF |
11 (0x0B) | 34 pF |
12 (0x0C) | 38 pF |
13 (0x0D) | 39 pF |
14 (0x0E) | Reserved |
15 (0x0F) | Reserved |
Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components.
Internal loop filter resistor R4 can be set according to Table 80.
R24[22:20] | RESISTANCE |
---|---|
0 (0x00) | 200 Ω |
1 (0x01) | 1 kΩ |
2 (0x02) | 2 kΩ |
3 (0x03) | 4 kΩ |
4 (0x04) | 16 kΩ |
5 (0x05) | Reserved |
6 (0x06) | Reserved |
7 (0x07) | Reserved |
Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components.
Internal loop filter resistor R3 can be set according to Table 81.
R24[18:16] | RESISTANCE |
---|---|
0 (0x00) | 200 Ω |
1 (0x01) | 1 kΩ |
2 (0x02) | 2 kΩ |
3 (0x03) | 4 kΩ |
4 (0x04) | 16 kΩ |
5 (0x05) | Reserved |
6 (0x06) | Reserved |
7 (0x07) | Reserved |
Increasing delay of PLL1_N_DLY will cause the outputs to lead from CLKinX. For use in 0-delay mode.
R24[14:12] | DEFINITION |
---|---|
0 (0x00) | 0 ps |
1 (0x01) | 205 ps |
2 (0x02) | 410 ps |
3 (0x03) | 615 ps |
4 (0x04) | 820 ps |
5 (0x05) | 1025 ps |
6 (0x06) | 1230 ps |
7 (0x07) | 1435 ps |
Increasing delay of PLL1_R_DLY will cause the outputs to lag from CLKinX. For use in 0-delay mode.
R24[10:8] | DEFINITION |
---|---|
0 (0x00) | 0 ps |
1 (0x01) | 205 ps |
2 (0x02) | 410 ps |
3 (0x03) | 615 ps |
4 (0x04) | 820 ps |
5 (0x05) | 1025 ps |
6 (0x06) | 1230 ps |
7 (0x07) | 1435 ps |
PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase error between the reference and feedback of PLL1 is less than specified time, then the PLL1 lock counter increments.
Refer to Digital Lock Detect Frequency Accuracy for more information.
R24[7:6] | DEFINITION |
---|---|
0 | 5.5 ns |
1 | 10 ns |
2 | 18.6 ns |
3 | 40 ns |
The DAC update clock frequency is the PLL1 phase detector frequency divided by the divisor listed in Table 85.
R25[31:22] | DIVIDE |
---|---|
0 (0x00) | Reserved |
1 (0x01) | 1 |
2 (0x02) | 2 |
3 (0x03) | 3 |
... | ... |
1,022 (0x3FE) | 1022 |
1,023 (0x3FF) | 1023 |
The reference and feedback of PLL1 must be within the window of phase error as specified by PLL1_WND_SIZE for this many phase detector cycles before PLL1 digital lock detect is asserted.
Refer to Digital Lock Detect Frequency Accuracy for more information.
R25[19:6] | VALUE |
---|---|
0 (0x0000) | Reserved |
1 (0x0001) | 1 |
2 (0x0002) | 2 |
3 (0x0003) | 3 |
... | ... |
16,382 (0x3FFE) | 16,382 |
16,383 (0x3FFF) | 16,383 |
PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase error between the reference and feedback of PLL2 is less than specified time, then the PLL2 lock counter increments. This value must be programmed to 2 (3.7 ns).
Refer to Digital Lock Detect Frequency Accuracy for more information.
R26[31:30] | DEFINITION |
---|---|
0 (0x00) | Reserved |
1 (0x01) | Reserved |
2 (0x02) | 3.7 ns |
3 (0x03) | Reserved |
Enabling the PLL2 reference frequency doubler allows for higher phase detector frequencies on PLL2 than would normally be allowed with the given VCXO or Crystal frequency.
Higher phase detector frequencies reduces the PLL N values which makes the design of wider loop bandwidth filters possible.
R26[29] | DESCRIPTION |
---|---|
0 | Reference frequency normal(1) |
1 | Reference frequency doubled (2x)(2) |
PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the negative charge pump polarity to be selected. Many VCOs use positive slope.
A positive slope VCO increases output frequency with increasing voltage. A negative slope VCO decreases output frequency with increasing voltage.
R26[28] | DESCRIPTION |
---|---|
0 | Negative Slope VCO/VCXO |
1 | Positive Slope VCO/VCXO |
This bit programs the PLL2 charge pump output current level. Table 90 also illustrates the impact of the PLL2 TRI-STATE bit in conjunction with PLL2_CP_GAIN.
R26[27:26] | PLL2_CP_TRI R26[5] |
CHARGE PUMP CURRENT (µA) |
---|---|---|
X | 1 | Hi-Z |
0 (0x00) | 0 | 100 |
1 (0x01) | 0 | 400 |
2 (0x02) | 0 | 1600 |
3 (0x03) | 0 | 3200 |
The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital lock detect is asserted.
Refer to Digital Lock Detect Frequency Accuracy for more information
R26[19:6] | VALUE |
---|---|
0 (0x00) | Reserved |
1 (0x01) | 1 |
2 (0x02) | 2 |
3 (0x003) | 3 |
... | ... |
16,382 (0x3FFE) | 16,382 |
16,383 (0x3FFF) | 16,383 |
This bit allows for the PLL2 charge pump output pin, CPout2, to be placed into TRI-STATE.
R26[5] | DESCRIPTION |
---|---|
0 | PLL2 CPout2 is active |
1 | PLL2 CPout2 is at TRI-STATE |
PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope.
A positive slope VCXO increases output frequency with increasing voltage. A negative slope VCXO decreases output frequency with increasing voltage.
R27[28] | DESCRIPTION |
---|---|
0 | Negative Slope VCO/VCXO |
1 | Positive Slope VCO/VCXO |
This bit programs the PLL1 charge pump output current level. Table 94 also illustrates the impact of the PLL1 TRI-STATE bit in conjunction with PLL1_CP_GAIN.
R26[27:26] | PLL1_CP_TRI R27[5] |
CHARGE PUMP CURRENT (µA) |
---|---|---|
X | 1 | Hi-Z |
0 (0x00) | 0 | 100 |
1 (0x01) | 0 | 200 |
2 (0x02) | 0 | 400 |
3 (0x03) | 0 | 1600 |
The pre-R dividers before the PLL1 R divider can be programmed such that when the active clock input is switched, the frequency at the input of the PLL1 R divider will be the same. This allows PLL1 to stay in lock without needing to re-program the PLL1 R register when different clock input frequencies are used. This is especially useful in the auto CLKin switching modes.
CLKinX_PreR_DIV | PROGRAMMING ADDRESS |
---|---|
CLKin1_PreR_DIV | R27[23:22] |
CLKin0_PreR_DIV | R27[21:20] |
R27[23:22, 21:20] | DIVIDE |
---|---|
0 (0x00) | 1 |
1 (0x01) | 2 |
2 (0x02) | 4 |
3 (0x03) | 8 |
The reference path into the PLL1 phase detector includes the PLL1 R divider. Refer to PLL Programming for more information on how to program the PLL dividers to lock the PLL.
The valid values for PLL1_R are shown in Table 97.
R27[19:6] | DIVIDE |
---|---|
0 (0x00) | Reserved |
1 (0x01) | 1 |
2 (0x02) | 2 |
3 (0x03) | 3 |
... | ... |
16,382 (0x3FFE) | 16,382 |
16,383 (0x3FFF) | 16,383 |
This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE.
R27[5] | DESCRIPTION |
---|---|
0 | PLL1 CPout1 is active |
1 | PLL1 CPout1 is at TRI-STATE |
The reference path into the PLL2 phase detector includes the PLL2 R divider.
Refer to PLL Programming for more information on how to program the PLL dividers to lock the PLL.
The valid values for PLL2_R are shown in Table 99.
R28[31:20] | DIVIDE |
---|---|
0 (0x00) | Not Valid |
1 (0x01) | 1(1). |
2 (0x02) | 2 |
3 (0x03) | 3 |
... | ... |
4,094 (0xFFE) | 4,094 |
4,095 (0xFFF) | 4,095 |
The feedback path into the PLL1 phase detector includes the PLL1 N divider.
Refer to PLL Programming for more information on how to program the PLL dividers to lock the PLL.
The valid values for PLL1_N are shown in Table 100.
R28[19:6] | DIVIDE |
---|---|
0 (0x00) | Not Valid |
1 (0x01) | 1 |
2 (0x02) | 2 |
... | ... |
4,095 (0xFFF) | 4,095 |
The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the frequency calibration routine which locks the internal VCO to the target frequency.
R29[26:24] | OSCin FREQUENCY |
---|---|
0 (0x00) | 0 to 63 MHz |
1 (0x01) | >63 MHz to 127 MHz |
2 (0x02) | >127 MHz to 255 MHz |
3 (0x03) | Reserved |
4 (0x04) | >255 MHz to 400 MHz |
When PLL2 phase detector frequency is greater than 100 MHz, set the PLL2_FAST_PDF to ensure proper operation of device.
R29[23] | PLL2 PDF |
---|---|
0 | Less than or equal to 100 MHz |
1 | Greater than 100 MHz |
During the frequency calibration routine, the PLL uses the divide value of the PLL2_N_CAL register instead of the divide value of the PLL2_N register to lock the VCO to the target frequency.
This is only used for internal PLL2 VCO modes.
NOTE: Unless in 0-delay mode or external VCO mode, PLL2_N_CAL should be set equal to PLL2_N.
Refer to PLL Programming for more information on how to program the PLL dividers to lock the PLL.
R29[22:5] | DIVIDE |
---|---|
0 (0x00) | Not Valid |
1 (0x01) | Not Valid |
2 (0x02) | 2 |
... | ... |
262,143 (0x3FFFF) | 262,143 |
If an internal VCO mode is used, programming Register 30 triggers the frequency calibration routine. This calibration routine will also generate a SYNC event. See Clock Output Synchronization (SYNC) for more details on a SYNC.
The PLL2 N Prescaler divides the output of the VCO as selected by Mode_MUX1VCO_MUX and is connected to the PLL2 N divider.
Refer to PLL Programming for more information on how to program the PLL dividers to lock the PLL.
R30[26:24] | DIVIDE VALUE |
---|---|
0 (0x00) | 8 |
1 (0x01) | 2 |
2 (0x02) | 2 |
3 (0x03) | 3 |
4 (0x04) | 4 |
5 (0x05) | 5 |
6 (0x06) | 6 |
7 (0x07) | 7 |
The feeback path into the PLL2 phase detector includes the PLL2 N divider.
Each time register 30 is updated via the MICROWIRE interface and the internal VCO is used, a frequency calibration routine runs to lock the VCO to the target frequency. During this calibration PLL2_N is substituted with PLL2_N_CAL.
Refer to PLL Programming for more information on how to program the PLL dividers to lock the PLL.
The valid values for PLL2_N are shown in Table 105.
R30[22:5] | DIVIDE |
---|---|
0 (0x00) | Not Valid |
1 (0x01) | 1(1) |
2 (0x02) | 2 |
... | |
262,143 (0x3FFFF) | 262,143 |
Sets the required state of the LEuWire pin when performing register readback.
Refer to Readback.
R31[21] | DEFINITION |
---|---|
0 | LE must be low for readback |
1 | LE must be high for readback |
Sets the address of the register to read back when performing readback.
When reading register 12, the READBACK_ADDR will be read back at R12[20:16].
When reading back from R31 bits 6 to 31 should be ignored. Only uWire_LOCK is valid.
Refer to Register Readback for more information on readback.
R31[20:16] | REGISTER |
---|---|
0 (0x00) | R0 |
1 (0x01) | R1 |
2 (0x02) | R2 |
3 (0x03) | R3 |
4 (0x04) | R4 |
5 (0x05) | R5 |
6 (0x06) | R6 |
7 (0x07) | R7 |
8 (0x08) | R8 |
9 (0x09) | Reserved |
10 (0x0A) | R10 |
11 (0x0B) | R11 |
12 (0x0C) | R12 |
13 (0x0D) | R13 |
14 (0x0E) | R14 |
15 (0x0F) | R15 |
16 (0x10) | R16 |
17 (0x11) | Reserved |
... | ... |
22 (0x16) | Reserved |
23 (0x17) | Reserved |
24 (0x18) | R24 |
25 (0x19) | R25 |
26 (0x1A) | R26 |
27 (0x1B) | R27 |
28 (0x1C) | R28 |
29 (0x1D) | R29 |
30 (0x1E) | R30 |
31 (0x1F) | R31 |
Setting uWire_LOCK will prevent any changes to uWire registers R0 to R30. Only by clearing the uWire_LOCK bit in R31 can the uWire registers be unlocked and written to once more.
It is not necessary to lock the registers to perform a readback operation.
R31[5] | STATE |
---|---|
0 | Registers unlocked |
1 | Registers locked, Write-protect |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
To assist customers in frequency planning and design of loop filters, Texas Instruments provides Clock Architect.
Each PLL of the LMK04208 requires a dedicated loop filter.
The loop filter for PLL1 must be connected to the CPout1 pin. Figure 21 shows a simple 2-pole loop filter. The output of the filter drives an external VCXO module or discrete implementation of a VCXO using a crystal resonator and external varactor diode. Higher order loop filters may be implemented using additional external R and C components. TI recommends that the loop filter for PLL1 result in a total closed loop bandwidth in the range of 10 Hz to 200 Hz. The design of the loop filter is application specific and highly dependent on parameters such as the phase noise of the reference clock, VCXO phase noise, and phase detector frequency for PLL1. TI's Clock Conditioner Owner’s Manual covers this topic in detail and Texas Instruments Clock Architect can be used to simulate loop filter designs for both PLLs. These resources may be found at:
Clock and Timing landing page.
As shown in Figure 21, the charge pump for PLL2 is directly connected to the optional internal loop filter components, which are normally used only if either a third or fourth pole is needed. The first and second poles are implemented with external components. The loop must be designed to be stable over the entire application-specific tuning range of the VCO. The designer should note the range of KVCO listed in the table of Electrical Characteristics and how this value can change over the expected range of VCO tuning frequencies. Because loop bandwidth is directly proportional to KVCO, the designer should model and simulate the loop at the expected extremes of the desired tuning range, using the appropriate values for KVCO.
When designing with the integrated loop filter of the LMK04208, considerations for minimum resistor thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4.
Both the integrated loop filter resistors (R3 and R4) and capacitors (C3 and C4) also restrict the maximum loop bandwidth. However, these integrated components do have the advantage that they are closer to the VCO and can therefore filter out some noise and spurs better than external components. For this reason, a common strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a wide enough loop bandwidth. In situations where spur requirements are very stringent and there is margin on phase noise, a feasible strategy would be to design a loop filter with integrated resistor values larger than their minimum value.
Both CLKin ports can be driven by differential signals. TI recommends that the input mode be set to bipolar (CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK04208 internally biases the input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 22 and Figure 23.
Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in Electrical Characteristics.
The CLKin pins of the LMK04208 can be driven using a single-ended reference clock source, for example, either a sine wave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case of the sine wave source that is expecting a 50-Ω load, TI recommends that AC coupling be used as shown in Figure 25 with a 50-Ω termination.
NOTE
The signal level must conform to the requirements for the CLKin pins listed in Electrical Characteristics. CLKinX_BUF_TYPE in Register 11 is recommended to be set to bipolar mode (CLKinX_BUF_TYPE = 0).
If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode (CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-mode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient.
When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:
It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK04208 , OSCin/OSCin* should be AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 40) This is only slightly different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage), not the driver.
For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 27.
For DC coupled operation of an LVPECL driver, terminate with 50 Ω to VCC - 2 V as shown in Figure 28. Alternatively, terminate with a Thevenin equivalent circuit (120-Ω resistor connected to VCC and an 82-Ω resistor connected to ground with the driver connected to the junction of the 120-Ω and 82-Ω resistors) as shown in Figure 29 for VCC = 3.3 V.
AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level.
When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 30.
Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 30 is modified by replacing the 50-Ω terminations to Vbias with a single 100-Ω resistor across the input pins of the receiver, as shown in Figure 31. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The previous figures employ a 0.10-µF capacitor. This value may need to be adjusted to meet the startup requirements for a particular application.
LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120-Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 32. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82-Ω resistor connected to VCC and a 120-Ω resistor connected to ground with the driver connected to the junction of the 82-Ω and 120-Ω resistors) is a valid termination as shown in Figure 32 for VCC = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 29.
A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal.
It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When DC coupling one of the LMK04208 clock LVPECL drivers, the termination should be 50 Ω to VCC - 2 V as shown in Figure 33. The Thevenin equivalent circuit is also a valid termination as shown in Figure 34 for Vcc = 3.3 V.
When AC coupling an LVPECL driver use a 120-Ω emitter resistor to provide a DC path to ground and ensure a 50-Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See Driving CLKin Pins with a Single-Ended Source). If the companion driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50-Ω termination of the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 35.
Calculating the value of the output dividers for use with the LMK04208 is simple due to the architecture of the LMK04208. That is, the VCO divider may be bypassed and the clock output dividers allow for even and odd output divide values from 2 to 1045. For most applications, TI recommends bypassing the VCO divider.
The procedure for determining the needed LMK04208 device and clock output divider values for a set of clock output frequencies is straightforward.
For example, given the following target output frequencies: 200 MHz, 120 MHz, and 25 MHz with a VCXO frequency of 40 MHz:
Refer to AN-1865, Frequency Synthesis and Planning for PLL Architectures for more information on this topic and LCM calculations.
To lock a PLL the divided reference and divided feedback from VCO or VCXO must result in the same phase detector frequency. The tables below illustrate how the divides are structured for the reference path (R) and feedback path (N) depending on the MODE of the device.
MODE | PLL1 PDF (R) = |
---|---|
All | CLKinX Frequency / (CLKinX_PreR_DIV * PLL1_R) |
MODE | VCO_MUX | OSCout | PLL1 PDF (N) = |
---|---|---|---|
Dual PLL, Internal VCO | — | Bypass | VCXO Frequency / PLL1_N |
— | Divided | VCXO Frequency / (OSCin_DIV * PLL1_N) | |
Dual PLL, Internal VCO, 0-Delay | Bypass | — | VCO Frequency / (CLKoutX_DIV * PLL1_N) (1) |
Divided | — | VCO Frequency / (VCO_DIV * CLKoutX_DIV * PLL1_N) (1) | |
Dual PLL, External VCO, 0-Delay | — | — | VCO Frequency / (CLKoutX_DIV * PLL1_N) (1) |
EN_PLL2_REF_2X | PLL2 PDF (R) = |
---|---|
Disabled | OSCin Frequency / PLL2_R(1)(2) |
Enabled | OSCin Frequency * 2 / PLL2_R(1)(2) |
MODE | VCO_MUX | PLL2 PDF (N) = |
---|---|---|
Dual PLL, Internal VCO | VCO | VCO Frequency / (PLL2_P * PLL2_N) |
Dual PLL, Internal VCO, 0-Delay | ||
Single PLL, Internal VCO | ||
Dual PLL, Internal VCO | VCO Divider | VCO Frequency / (VCO_DIV * PLL2_P * PLL2_N) |
Dual PLL, Internal VCO, 0-Delay | ||
Single PLL, Internal VCO | ||
Dual PLL, External VCO | — | VCO Frequency / (PLL2_P * PLL2_N) |
Dual PLL External VCO, 0-Delay | ||
Single PLL, External VCO | ||
Single PLL, Internal VCO, 0-Delay | VCO | VCO Frequency / (CLKoutX_DIV * PLL2_N) |
VCO Divider | VCO Frequency / (VCO_DIV * CLKoutX_DIV * PLL2_N) |
MODE | VCO_MUX | PLL2 PDF (N_CAL) = |
---|---|---|
All Internal VCO Modes | VCO | VCO Frequency / (PLL2_P * PLL2_N_CAL) |
VCO Divider | VCO Frequency / (VCO_DIV * PLL2_P * PLL2_N_CAL) |
To program PLL2 to lock an LMK04208 using Dual PLL mode to a VCO frequency of 3000 MHz using a 40 MHz VCXO reference, first determine the total PLL2 N divide value. This is VCO Frequency / PLL2 phase detector frequency. This example assumes the PLL2 reference frequency doubler is enabled and a PLL2 R divide value of 2 (see Note 1 in Table 111) which results in PLL2 phase detector frequency the same as PLL2 reference frequency (40 MHz). 3000 MHz / 40 MHz = 75, so the total PLL2 N divide value is 75.
The dividers in the PLL2 N feedback path for Dual PLL mode include PLL2_P and PLL2_N. PLL2_P can be programmed from 2 to 8, including both even and odd values. PLL2_N can be programmed from 1 to 263,143, including both even and odd values. Since the total PLL2 N divide value of 75 contains the factors 3, 5, and 5, it would be allowable to program PLL2_P to 3 or 5. It is simplest to use the smallest divide, so PLL2_P = 3, and PLL2_N = 25 which results in a Total PLL2 N = 75.
For this example and in most cases, PLL2_N_CAL will have the same value as PLL2_N. However when using Single PLL mode with 0-delay, the values will differ. When using an external VCO, PLL2_N_CAL value is unused.
The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true. When the holdover exit event occurs, the device will exit holdover mode.
EVENT | PLL | WINDOW SIZE | LOCK COUNT |
---|---|---|---|
PLL1 Locked | PLL1 | PLL1_WND_SIZE | PLL1_DLD_CNT |
PLL2 Locked | PLL2 | PLL2_WND_SIZE | PLL2_DLD_CNT |
Holdover exit | PLL1 | PLL1_WND_SIZE | HOLDOVER_DLD_CNT |
For a digital lock detect event to occur there must be a “lock count” number of phase detector cycles of PLLX during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable "window size." Since there must be at least "lock count" phase detector events before a lock event occurs, a minimum digital lock event time can be calculated as "lock count" / fPDX where X = 1 for PLL1 or 2 for PLL2.
By using Equation 5, values for a "lock count" and "window size" can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs:
The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size" by "lock count".
If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by "window size", then the “lock count” value is reset to 0.
The minimum time for PLL2 digital lock to be asserted can be calculated by Equation 6:
Given a PLL2 phase detector frequency of 40 MHz and PLL2_DLD_CNT value of 10,000, the minimum digital lock detect time of PLL2 will be 10,000 / 40 MHz = 250 μs.
This section explains how to calculate the dynamic digital delay for any divide value.
Dynamic digital delay allows the time offset between two or more clock outputs to be adjusted with no or minimal interruption of clock outputs. Since the clock outputs are operating at a known frequency, the time offset can also be expressed as a phase shift. When dynamically adjusting the digital delay of clock outputs with different frequencies the phase shift should be expressed in terms of the higher frequency clock. The step size of the smallest time adjustment possible is equal to half the period of the Clock Distribution Path, which is the VCO frequency (Equation 3) or the VCO frequency divided by the VCO divider (Equation 4) if not bypassed. The smallest degree phase adjustment with respect to a clock frequency will be 360 * the smallest time adjustment * the clock frequency. The total number of phase offsets that the LMK04208 is able to achieve using dynamic digital delay is equal 1 / (higher clock frequency * the smallest phase adjustment).
Equation 7 calculates the digital delay value that must be programmed for a synchronizing clock to achieve a 0 time/phase offset from the qualifying clock. Once this digital delay value is known, it is possible to calculate the digital delay value for any phase offset. The qualifying clock for dynamic digital delay is selected by the FEEDBACK_MUX. When dynamic digital delay is engaged with same clock output used for the qualifying clock and the new synchronized clock, it is termed relative dynamic digital delay since causing another SYNC event with the same digital delay value will offset the clock by the same phase once again. The important part of relative dynamic digital delay is that the CLKoutX_HS must be programmed correctly when the SYNC event occurs (Table 6). This can result in needing to program the device twice. Once to set the new CLKoutX_DDLY with CLKoutX_HS as required for the SYNC event, and again to set the CLKoutX_HS to its desired value.
Digital delay values are programmed using the CLKoutX_DDLY and CLKoutX_HS registers as shown in Equation 8. For example, to achieve a digital delay of 13.5, program CLKoutX_DDLY = 14 and CLKoutX_HS = 1.
Equation 7 uses the ceiling operator. To find the ceiling of a fractional number round up. An integer remains the same value.
Note: since the digital delay value for 0 time/phase offset is a function of the qualifying clock's divide value, the resulting digital delay value can be used for any clock output operating at any frequency to achieve a 0 time/phase offset from the qualifying clock. Therefore the calculated time shift table will also be the same as in Table 115.
Consider a system with:
For this system the minimum time adjustment is ~0.16667 ns, which is 0.5 / (3000 MHz). Since the higher frequency is 300 MHz, phase adjustments will be calculated with respect to the 300 MHz frequency. The 0.25 ns minimum time adjustment results in a minimum phase adjustment of 18 degrees, which is 360 degrees / 200 MHz * 0.25 ns.
To calculate the digital delay value to achieve a 0 time/phase shift of CLKout2 when CLKout0 is the qualifying clock. Solve Equation 7 using the divide value of 10. To solve the equation 16/10 = 1.6, the ceiling of 1.6 is 2. Then to finish solving the equation solve (2 + 0.5) * 10 - 11.5 = 13.5. A digital delay value of 13.5 is programmed by setting CLKout1_DDLY = 14 and CLKout1_HS = 1.
To calculate the digital delay value to achieve a 0 time/phase shift of CLKout0 when CLKout2 is the qualifying clock, solve Equation 7 using the divide value of CLKout2, which is 20. This results in a digital delay of 18.5 which is programmed as CLKout0_DDLY = 19 and CLKout0_HS = 1.
Once the 0 time/phase shift digital delay programming value is known a table can be constructed with the digital delay value to be programmed for any time/phase offset by decrementing or incrementing the digital delay value by 0.5 for the minimum time/phase adjustment.
A complete filled out table for use of CLKout0 as the qualifying clock is shown in Table 115. It was created by entering a digital delay of 13.5 for 0 degree phase shift, then decrementing the digital delay down to the minimum value of 4.5. Since this did not result in all the possible phase shifts, the digital delay was then incremented from 13.5 to 14.0 to complete all possible phase shifts.
DIGITAL DELAY |
CALCULATED TIME SHIFT (ns) |
RELATIVE TIME SHIFT to 300 MHz (ns) |
PHASE SHIFT of 300 MHz (Degrees) |
---|---|---|---|
4.5 | -3.0 | 0.333... | 36 |
5 | -2.833... | 0.5 | 54 |
5.5 | -2.666... | 0.666... | 72 |
6 | -2.5 | 0.833... | 90 |
6.5 | -2.333 | 1.0 | 108 |
7 | -2.166 | 1.166... | 126 |
7.5 | -2.0 | 1.333... | 144 |
8 | -1.833 | 1.5 | 162 |
8.5 | -1.666... | 1.666... | 180 |
9 | -1.5 | 1.833... | 198 |
9.5 | -1.333... | 2.0 | 216 |
10 | -1.166... | 2.166... | 234 |
10.5 | -1.0 | 2.333... | 252 |
11 | -0.833... | 2.5 | 270 |
11.5 | -0.666... | 2.666... | 288 |
12 | -0.5 | 2.833... | 306 |
12.5 | -0.333... | 3.0 | 324 |
13 | -0.166... | 3.166... | 342 |
13.5 | 0 | 0 | 0 |
14 | 0.166... | 0.166... | 18 |
14.5 | 0.333... | 0.333... | 36 |
Observe that the digital delay value of 4.5 and 14.5 will achieve the same relative time shift/phase delay. However programming a digital delay of 14.5 will result in a clock off time for the synchronizing clock to achieve the same phase time shift/phase delay.
Digital delay value is programmed as CLKoutX_DDLY - (0.5 * CLKoutX_HS). So to achieve a digital delay of 13.5, program CLKoutX_DDLY = 14 and CLKoutX_HS = 1. To achieve a digital delay of 14, program CLKoutX_DDLY = 14 and CLKoutX_HS = 0.
The LMK04208 features supporting circuitry for a discretely implemented oscillator driving the OSCin port pins. Figure 36 illustrates a reference design circuit for a crystal oscillator:
This circuit topology represents a parallel resonant mode oscillator design. When selecting a crystal for parallel resonance, the total load capacitance, CL, must be specified. The load capacitance is the sum of the tuning capacitance (CTUNE), the capacitance seen looking into the OSCin port (CIN), and stray capacitance due to PCB parasitics (CSTRAY), and is given by Equation 9.
CTUNE is provided by the varactor diode shown in Figure 36, Skyworks model SMV1249-074LF. A dual diode package with common cathode provides the variable capacitance for tuning. The single diode capacitance ranges from approximately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range of the dual package (anode to anode) is approximately 15.5 pF at 3 V to 1.7 pF at 0.3 V. The desired value of VTUNE applied to the diode should be VCC/2, or 1.65 V for VCC = 3.3 V. The typical performance curve from the data sheet for the SMV1249-074LF indicates that the capacitance at this voltage is approximately 6 pF (12 pF / 2).
The nominal input capacitance (CIN) of the LMK04208 OSCin pins is 6 pF. The stray capacitance (CSTRAY) of the PCB should be minimized by arranging the oscillator circuit layout to achieve trace lengths as short as possible and as narrow as possible trace width (50 Ω characteristic impedance is not required).
As an example, assume that CSTRAY is 4 pF. The total load capacitance is nominally:
Consequently the load capacitance specification for the crystal in this case should be nominally 14 pF.
The 2.2-nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the 4.7-kΩ and 10-kΩ resistors. The value of these coupling capacitors should be large, relative to the value of CTUNE (CC1 = CC2 >> CTUNE), so that CTUNE becomes the dominant capacitance.
For a specific value of CL, the corresponding resonant frequency (FL) of the parallel resonant mode circuit is:
where
The normalized tuning range of the circuit is closely approximated by:
CL1, CL2 = The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one component of the load. FCL1, FCL2 = parallel resonant frequencies at the extremes of the circuit’s load capacitance range.
A common range for the pullability ratio, C0/C1, is 250 to 280. The ratio of the load capacitance to the shunt capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning range because this allows the scale factors related to the load capacitance to dominate.
Examples of the phase noise and jitter performance of the LMK04208 with a crystal oscillator are shown in Table 116. This table illustrates the clock output phase noise when a 20.48-MHz crystal is paired with PLL1. Performance of other LMK04208 devices will be similar.
INTEGRATION BANDWIDTH | CLOCK OUTPUT TYPE | PLL2 PDF = 20.48 MHz (EN_PLL2_REF2X = 0, XTAL_LVL = 3) |
PLL2 PDF = 40.96 MHz (EN_PLL2_REF2X = 1, XTAL_LVL = 3) |
|
---|---|---|---|---|
fCLK = 245.76 MHz | fCLK = 122.88 MHz | fCLK = 245.76 MHz | ||
RMS JITTER (fs, RMS) | ||||
100 Hz – 20 MHz | LVCMOS | 374 | 412 | 382 |
LVDS | 419 | 421 | 372 | |
LVPECL 1.6 Vpp | 460 | 448 | 440 | |
10 kHz – 20 MHz | LVCMOS | 226 | 195 | 190 |
LVDS | 231 | 205 | 194 | |
LVPECL 1.6 Vpp | 226 | 191 | 188 | |
PHASE NOISE (dBc/Hz) | ||||
Offset | Clock Output Type | PLL2 PDF = 20.48 MHz (EN_PLL2_REF2X = 0, XTAL_LVL = 3) |
PLL2 PDF = 40.96 MHz (EN_PLL2_REF2X = 1, XTAL_LVL = 3) |
|
fCLK = 245.76 MHz | fCLK = 122.88 MHz | fCLK = 245.76 MHz | ||
100 Hz | LVCMOS | -87 | -93 | -87 |
LVDS | -86 | -91 | -86 | |
LVPECL 1.6 Vpp | -86 | -92 | -85 | |
1 kHz | LVCMOS | -115 | -121 | -115 |
LVDS | -115 | -123 | -116 | |
LVPECL 1.6 Vpp | -114 | -122 | -116 | |
10 kHz | LVCMOS | -117 | -128 | -122 |
LVDS | -117 | -128 | -122 | |
LVPECL 1.6 Vpp | -117 | -128 | -122 | |
100 kHz | LVCMOS | -130 | -135 | -129 |
LVDS | -130 | -135 | -129 | |
LVPECL 1.6 Vpp | -129 | -135 | -129 | |
1 MHz | LVCMOS | -150 | -154 | -148 |
LVDS | -149 | -153 | -148 | |
LVPECL 1.6 Vpp | -150 | -154 | -148 | |
40 MHz | LVCMOS | -159 | -162 | -159 |
LVDS | -157 | -159 | -157 | |
LVPECL 1.6 Vpp | -159 | -161 | -159 |
Example crystal specifications are presented in Table 117.
PARAMETER | VALUE |
---|---|
Nominal Frequency (MHz) | 20.48 |
Frequency Stability, T = 25 °C | ± 10 ppm |
Operating temperature range | -40 °C to +85 °C |
Frequency Stability, -40 °C to +85 °C | ± 15 ppm |
Load Capacitance | 14 pF |
Shunt Capacitance (C0) | 5 pF Maximum |
Motional Capacitance (C1) | 20 fF ± 30% |
Equivalent Series Resistance | 25 Ω Maximum |
Drive level | 2 mWatts Maximum |
C0/C1 ratio | 225 typical, 250 Maximum |
See Figure 37 for a representative tuning curve.
The tuning curve achieved in the user's application may differ from the curve shown above due to differences in PCB layout and component selection.
This data is measured on the bench with the crystal integrated with the LMK04208. Using a voltmeter to monitor the VTUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is valid.
The curve shows over the tuning voltage range of 0.3 VDC to 3.0 VDC, the frequency range is -140 to +91 ppm; or equivalently, a tuning range of -2850 Hz to +1850 Hz. The measured tuning voltage at the nominal crystal frequency (20.48 MHz) is 1.7 V. Using the diode data sheet tuning characteristics, this voltage results in a tuning capacitance of approximately 6.5 pF.
The tuning curve data can be used to calculate the gain of the oscillator (KVCO). The data used in the calculations is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal frequency (20.48 MHz). For a well designed circuit, this is the most likely operating range. In this case, the tuning range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to calculate the ratio:
ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:
A second method uses the tuning data in units of ppm:
FNOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:
In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal should conform to the specifications listed in the table of Electrical Characteristics.
It is also important to select a crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the crystal, voltage and equivalent series resistance (ESR).
For more complete coverage of crystal oscillator design, see:
Clocks and Timers or AN-1939 Crystal Based Oscillator Design with the LMK04000 Family.
Normal use case of the LMK04208 device is as a dual loop jitter cleaner. This section will discuss a design example to illustrate the various functional aspects of the LMK04208 device.
Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES, and an LO. The input clock will be a recovered clock which needs jitter cleaning. The FPGA clock should have a clock output on power up. A summary of clock input and output requirements are as follows:
Clock Input:
Clock Outputs:
It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The following information reviews the steps to produce this design.
Design of all aspects of the LMK04208 are quite involved and software has been written to assist in part selection, part programming, loop filter design, and simulation. This design procedure will give a quick outline of the process.
Note that this information is current as of the date of the release of this datasheet. Design tools receive continuous improvements to add features and improve model accuracy. Refer to software instructions or training for latest features.
Some additional information on each part of the design procedure for the RRU example is below.
Use the WEBENCH Clock Architect Tool. Enter the required frequencies and formats into the tool. To use this device, find a solution using the LMK04208.
When viewing resulting solutions, it is possible to narrow the parts used in the solution by setting a filter.
Filtering of a specific device can be done by selecting the device from the filter combo box. Also, regular expressions can be typed into filter combo box. LMK04208 will filter for only the LMK04208 device.
To simulate single loop solutions with dual loop device, set PLL1 loop filter to a very narrow or "0 Hz LBW."
In this example, the LCM(245.76 MHz, 983.04 MHz, 122.88 MHz) = 983.04 MHz. A valid VCO frequency for LMK04208 is 2949.12 MHz = 3 * 983.04 MHz. Therefore the LMK04208 may be used to produce these output frequencies.
The tools automatically configure the simulation to meet the input and output frequency requirements given and make assumptions about other parameters to give some default simulations. The assumptions made are to maximize input frequencies, phase detector frequencies, and charge pump currents while minimizing VCO frequency and divider values.
PLL1 outputs have the best phase noise performance for LO references. As such OSCout, or CLKout3/CLKout4 (with CLKout#_OSCin_Sel field selecting OSCin clock source) can be used to provide the 122.88 MHz LO reference clock. To achieve this with a 245.76 MHz VCXO the OSCout_DIV can be set to 2 to provide 122.88 MHz at OSCout. CLKout3/4_DIV can be set to 2 for 122.88 MHz output if LO references are clocked from CLKout3/4.
In the next section it is determined that for the POR clock, a 122.88 MHz VCXO will be used. This means no division will be needed to provide 122.88 MHz.
If OSCout is to be used for LVDS POR 122.88 MHz clock, the POR value of the OSCout_DIV is 1, so a 122.88 MHz VCXO frequency must be chosen. This may be desired anyway since the phase detector frequency is limited to 122.88 MHz and lower frequency VCXOs tend to cost less. With this change the OSCin frequency and phase detector frequency are the same, so the doubler must be enabled and the PLL2 R divider programmed = 2 to follow the rule stated in PLL2 Frequency Doubler.
Note: it is possible to set the PLL2 R = 0.5 to simulate the doubler in-case lower frequency VCXOs would like to be simulated. For example a 61.44 MHz VCXO could be used while retaining a 122.88 MHz phase detector frequency. However, it would reduce the LO reference frequency and POR clock frequency to 61.44 MHz.
At this time, the VCXO frequency and phase detector frequency is chosen, so loop filter design may begin.
The PLL structure for the LMK04208 is illustrated in Loop Filter.
At this time the user may choose to make adjustments to the simulation tools for more accurate simulations to their application. For example:
For this example, for PLL1 to perform jitter cleaning and to minimize jitter from PLL2 used for frequency multiplication:
The next two sections will discuss PLL1 and PLL2 loop filter design specific to this example using default phase noise profiles.
NOTE
Clock Architect provides some recommend loop filters upon first load of the simulation. Anytime PLL related inputs change like an input phase noise, charge pump current, divider values, and so forth. it is best to re-design the PLL1 loop filter to the recommended design or your desired parameters. After PLL1, then update the PLL2 loop filter in the same way to keep the loop filters designed and optimized for the application. Since PLL1 loop filter design may impact PLL2 loop filter design, be sure to update the designs in order.
For this example, in the Clock Architect tool update the loop bandwidth for 0.05 kHz and the phase margin for 50 degrees and press "Choose RC Components for me." With the 30.72 MHz phase detector frequency and 1.6 mA charge pump; the designed loop filter's largest capacitor, C2, is 27 µF. Supposing a goal of < 10 µF; setting PLL1 R = 4 and pressing the calculate again shows that C2 is 6.8 µF. Suppose that a reduction to < 1 µF is desired, continuing to increase the PLL1 R to 8 resulting in a phase detector frequency of 3.84 MHz and reducing the charge pump current from 1.6 mA to 0.4 mA and calculating again shows that C2 is 820 nF. As N was increased and charge pump decreased, this final design has R2 = 12 kΩ. The first design with low N value and high charge pump current result in R2 = 390 Ω. The impact of the thermal resistance is calculated in the tool. Viewing the simulation of the loop filter with the 12-kΩ resistor shows that the thermal noise in the loop is not impacting performance.
It may be desired to design a 3rd order loop filter for additional attenuation input noise and spurs
With the PLL1 loop filter design complete, PLL2's loop filter is ready to be designed.
In Clock Architect, select LOOPFILTER2 tab under Loop Filters tab. Click "Choose RC Components for me." For PLL2's loop filter maximum phase detector frequency and maximum charge pump current are typically used. Typically the jitter integration bandwidth includes the loop filter bandwidth for PLL2. The recommended loop filter by the tools are designed to minimize jitter. The integrated loop filter components are minimized with this recommendation as to allow maximum flexibility in achieve wide loop bandwidths for low PLL noise. With the recommended loop filter calculated, this loop filter is ready to be simulated.
If using integrated components is desired, make adjustments to the integrated components. The effective loop bandwidth and phase margin with these updates is calculated every time "Update Actual Loop Parameters" is clicked. The integrated loop filter components are good to use when attempting to eliminate some spurs since they provide filtering after the bond wires. The recommended procedure is to increase C3/C4 capacitance, then R3/R4 resistance. Large R3/R4 resistance can result in degraded VCO phase noise performance.
At this time Clock Architect only assign outputs to specific clock outputs numerically; not necessarily by optimum configuration. The user may wish to make some educated re-assignment of outputs.
During device configuration, some output assignment was discussed since it impacted the part's configuration relating to loop filter design, such as:
Since CLKout3 and CLKout4 have a mux allowing them to be driven by the VCXO and due there is a chance for some 122.88 MHz crosstalk from the VCXO. The 122.88 MHz SERDES clock will be placed on CLKout4 since it will not be sensitive to crosstalk as it is operating at the same frequency.
Three converter clocks still need to be assigned. The 245.76 MHz ADC clock and two 983.04 MHz DAC. There are four remaining clock outputs. To maximize distance of the ADC clock from other clocks which could create sub-harmonic spurs, CLKout0 is chosen for ADC at 245.76 MHz clock. CLKout1 and CLKout2 are chosen for the DAC 983.04 MHz clocks. Because the ADC clock is often the most sensitive to sub-harmonic spurs, the goal was to place the ADC clock as far as possible from other clocks which could result in sub-harmonic spurs.
Digital lock time for PLL1 will ultimately depend upon the programming of the PLL1_DLD_CNT register as discussed in Digital Lock Detect Frequency Accuracy. Since the PLL1 phase detector frequency in this example is 3.84 MHz, the lock time will = 1 / (PLL1_DLD_CNT * 3.84 MHz)
Digital lock time for PLL1 if PLL1_DLD_CNT = 10000 is just over 2.6 ms. When using holdover, it is very important to program the PLL1_DLD_CNT to a value large enough to prevent false digital lock detect signals.
If PLL1_DLD_CNT is too small, when the device exits holdover and is re-locking, the DLD will go high while the phase of the reference and feedback are within the specified window size because the programmed PLL1_DLD_CNT will be satisfied. However, if the loop has not yet settled to without the window size, when the phases of the reference and feedback once again exceed the window size, the DLD will return low. Provided that DISABLE_DLD1_DET = 0, the device once again enter holdover. Assuming that the reference clock is valid because holdover was just exited, the exit criteria will again be met, holdover will exit, and PLL1 will start locking. Unfortunately, the same sequence of events will repeat resulting in oscillation out-of and back-into holdover. Setting the PLL1_DLD_CNT to an appropriately large value prevents chattering of the PLL1 DLD signal and stable holdover operation can be achieved.
Refer to Digital Lock Detect Frequency Accuracy for more detail on calculating exit times and how the PLL1_DLD_CNT and PLL1_WND_SIZE work together.
For this example, when the recovered clock is lost, the goal is to set the VCXO to Vcc/2 until the recovered clock returns. Holdover Mode contains detailed information on how to program holdover.
To achieve the above goal, fixed holdover will be used. Program:
The TICS Pro software is used to program the LMK04208 evaluation board using the LMK04208 profile. It also allows the exporting of a register map which can be used to program the device to the user’s desired configuration.
Once a configuration has been achieved using the TICS Pro to meet the requested input/output frequencies with the desired performance, the TICS Pro software is manually updated with this information to meet the required application. At this time no automatic import exists.
Figure 40 and Figure 41 show an LMK04208 device with external circuitry for clocking and for power supply to serve as a guideline for good practices when designing with the LMK04208. Refer to Pin Connection Recommendations for more details on the pin connections and bypassing recommendations. Also refer to the evaluation board in LMK0480x Evaluation Board Instructions. PCB design will also play a role in device performance. As discussed in PLL LO Reference , the LO clocks at 122.88 MHz may be moved to CLKout5 if the VCXO frequency will support 122.88 MHz output.
Figure 40 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-ended. These options are discussed later in the data sheet.
See Loop Filter for more information on PLL1 and PLL2 loop filters.
In the system shown in Figure 40, LVPECL clocks are AC coupled via 0.1 µF capacitors and LVDS clocks are DC coupled. Some clock outputs are depicted as LVPECL with 240-Ω emitter resistors and some clock outputs as LVDS. The appropriate output termination on each output should be implemented according to the output format to be programmed by the user. Later sections of this data sheet illustrate alternative methods for AC coupling, DC coupling, and terminating the clock outputs. PCB design will influence crosstalk performance. Tightly coupled clock traces will have less crosstalk than loosely coupled clock traces. Also proximity to other clocks traces will influence crosstalk.
Figure 41 shows an example decoupling and bypassing scheme for the LMK04208, which could apply to configuration shown in Figure 40. The ferrite beads and capacitors drawn in dotted lines are optional (see Pin Connection Recommendations). Two power planes are used in these example designs, one for the clock outputs and one for PLL circuits. It is possible to reduce the number of decoupling components by tying together clock output Vcc pins for CLKouts that share the same frequency or otherwise can tolerate potential crosstalk between outputs with different frequencies. In the two examples, Vcc2 and Vcc3 can be tied together since CLKout1 and CLKout2 will operate at the same frequencies. Vcc10, Vcc11, and Vcc12 can be tied together since potential crosstalk between the FPGA/SerDes clocks and low-frequency synchronization clocks will not impact the performance of these digital interfaces, which typically have less stringent jitter requirements. PCB design will influence impedance to the supply. Vias and traces will increase the impedance to the power supply. Ensure good direct return current paths.
When using an LVPECL output it is not recommended to place a capacitor to ground on the output as might be done when using a capacitor input LC lowpass filter. The capacitor will appear as a short to the LVPECL output drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large switching currents can result in the following:
When CLKuWire and DATAuWire toggle and an internal VCO mode is used, there may some spurious content on the phase noise plot related to the frequency of the CLKuWire and DATAuWire pins.