SNAS689A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input for pin select mode.
The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input for pin select mode.
If the CLKin_SELX_TYPE is set as output, the pin input value is considered Low.
The polarity of CLKin_SEL0 and CLKin_SEL1 input pins can be inverted with the CLKin_SEL_INV bit.
Table 5 defines which input clock is active depending on CLKin_SEL0 and CLKin_SEL1 state.
PIN CLKin_SEL1 | PIN CLKin_SEL0 | ACTIVE CLOCK |
---|---|---|
Low | Low | CLKin0 |
Low | High | CLKin1 |
High | Low | CLKin2 |
High | High | Holdover |
The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX = 1) that could be switched to.