SNAS689A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
From Table 82 the current consumption can be calculated for any configuration. Data below is typical and not assured.
BLOCK | TEST CONDITION | TYPICAL ICC
(mA) |
POWER
DISSIPATED IN DEVICE (mW) |
||
---|---|---|---|---|---|
CORE and FUNCTIONAL BLOCKS | |||||
Core | Dual-loop, internal VCO0 | PLL1 and PLL2 locked | 131.5 | 433.95 | |
VCO | VCO1 is selected | LMK04228 | 13.5 | 44.55 | |
OSCin Doubler | Doubler is enabled | EN_PLL2_REF_2X = 1 | 3 | 9.9 | |
CLKin | Any one of the CLKinX is enabled | 4.9 | 16.17 | ||
Holdover | Holdover is enabled | HOLDOVER_EN = 1 | 1.3 | 4.29 | |
Hitless switch is enabled | HOLDOVER_HITLESS_SWITCH = 1 | 0.9 | 2.97 | ||
Track mode | TRACK_EN = 1 | 2.5 | 8.25 | ||
SYNC_EN = 1 | Required for SYNC and SYSREF functionality | 7.6 | 25.08 | ||
SYSREF | Enabled | SYSREF_PD = 0 | 27.2 | 89.76 | |
Pulser is enabled | SYSREF_PLSR_PD = 0 | 4.1 | 13.53 | ||
SYSREF pulses mode | SYSREF_MUX = 2 | 3 | 9.9 | ||
SYSREF continuous mode | SYSREF_MUX = 3 | 3 | 9.9 | ||
CLOCK GROUP | |||||
Enabled | Any one of the CLKoutX_Y_PD = 0 | 20.1 | 66.33 | ||
IDL | Any one of the CLKoutX_Y_IDL = 1 | 2.2 | 7.26 | ||
ODL | Andy one of the CLKoutX_Y_ODL = 1 | 3.2 | 10.56 | ||
Clock Divider | Divider only | DCLKoutX_MUX = 0 | 13.6 | 44.88 | |
Divider + DCC + HS | DCLKoutX_MUX = 1 | 17.7 | 58.41 | ||
Analog Delay + Divider | DCLKoutX_MUX = 3 | 13.6 | 44.88 | ||
CLOCK OUTPUT BUFFERS | |||||
LVDS | 100-Ω differential termination | 6 | 19.8 | ||
OSCout BUFFERS | |||||
LVDS | 100-Ω differential termination | 18.5 | 61.05 | ||
LVCMOS | LVCMOS pair | 150 MHz | 42.6 | 140.58 | |
LVCMOS single | 150 MHz | 27 | 89.1 |