SNAS689A October   2017  – July 2019 LMK04228

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Timing Diagram
  8. 8 Parameter Measurement Information
    1. 8.1 Charge Pump Current Specification Definitions
      1. 8.1.1 Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
      2. 8.1.2 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
      3. 8.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature
    2. 8.2 Differential Voltage Measurement Terminology
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Jitter Cleaning
      2. 9.1.2 JEDEC JESD204B Support
      3. 9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
      4. 9.1.4 VCXO- and Crystal-Buffered Output
      5. 9.1.5 Frequency Holdover
      6. 9.1.6 PLL2 Integrated Loop Filter Poles
      7. 9.1.7 Internal VCOs
      8. 9.1.8 Clock Distribution
        1. 9.1.8.1 Device Clock Divider
        2. 9.1.8.2 SYSREF Clock Divider
        3. 9.1.8.3 Device Clock Delay
        4. 9.1.8.4 SYSREF Delay
        5. 9.1.8.5 Programmable Output Formats
        6. 9.1.8.6 Clock Output Synchronization
      9. 9.1.9 Status Pins
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 SYNC/SYSREF
      2. 9.3.2 JEDEC JESD204B
        1. 9.3.2.1 How to Enable SYSREF
          1. 9.3.2.1.1 Setup of SYSREF Example
          2. 9.3.2.1.2 SYSREF_CLR
        2. 9.3.2.2 SYSREF Modes
          1. 9.3.2.2.1 SYSREF Pulser
          2. 9.3.2.2.2 Continuous SYSREF
          3. 9.3.2.2.3 SYSREF Request
      3. 9.3.3 Digital Delay
        1. 9.3.3.1 Fixed Digital Delay
          1. 9.3.3.1.1 Fixed Digital Delay Example
      4. 9.3.4 SYSREF to Device Clock Alignment
      5. 9.3.5 Input Clock Switching
        1. 9.3.5.1 Input Clock Switching - Manual Mode
        2. 9.3.5.2 Input Clock Switching - Pin Select Mode
          1. 9.3.5.2.1 Configuring Pin Select Mode
        3. 9.3.5.3 Input Clock Switching - Automatic Mode
          1. 9.3.5.3.1 Starting Active Clock
      6. 9.3.6 Digital Lock Detect
        1. 9.3.6.1 Calculating Digital Lock Detect Frequency Accuracy
      7. 9.3.7 Holdover
        1. 9.3.7.1 Enable Holdover
          1. 9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 9.3.7.1.2 Tracked CPout1 Holdover Mode
        2. 9.3.7.2 During Holdover
        3. 9.3.7.3 Exiting Holdover
        4. 9.3.7.4 Holdover Frequency Accuracy and DAC Performance
        5. 9.3.7.5 Holdover Mode - Automatic Exit of Holdover
    4. 9.4 Programming
      1. 9.4.1 Recommended Programming Sequence
        1. 9.4.1.1 SPI LOCK
        2. 9.4.1.2 SYSREF_CLR
    5. 9.5 Register Maps
      1. 9.5.1 Register Map for Device Programming
      2. 9.5.2 Device Register Descriptions
        1. 9.5.2.1 System Functions
          1. 9.5.2.1.1 RESET, SPI_3WIRE_DIS
          2. 9.5.2.1.2 POWERDOWN
          3. 9.5.2.1.3 ID_DEVICE_TYPE
          4. 9.5.2.1.4 ID_PROD[15:8], ID_PROD
          5. 9.5.2.1.5 ID_MASKREV
          6. 9.5.2.1.6 ID_VNDR[15:8], ID_VNDR
        2. 9.5.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
          1. 9.5.2.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
          2. 9.5.2.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
          3. 9.5.2.2.3 DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
          4. 9.5.2.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
          5. 9.5.2.2.5 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
          6. 9.5.2.2.6 DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
          7. 9.5.2.2.7 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
        3. 9.5.2.3 SYSREF, SYNC, and Device Config
          1. 9.5.2.3.1 VCO_MUX, OSCout_FMT
          2. 9.5.2.3.2 SYSREF_CLKin0_MUX, SYSREF_MUX
          3. 9.5.2.3.3 SYSREF_DIV[12:8], SYSREF_DIV[7:0]
          4. 9.5.2.3.4 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
          5. 9.5.2.3.5 SYSREF_PULSE_CNT
          6. 9.5.2.3.6 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
          7. 9.5.2.3.7 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
          8. 9.5.2.3.8 SYNC_DISSYSREF, SYNC_DISX
          9. 9.5.2.3.9 Fixed Register
        4. 9.5.2.4 (0x146 - 0x149) CLKin Control
          1. 9.5.2.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
          2. 9.5.2.4.2 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
          3. 9.5.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
          4. 9.5.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
        5. 9.5.2.5 RESET_MUX, RESET_TYPE
        6. 9.5.2.6 (0x14B - 0x152) Holdover
          1. 9.5.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
          2. 9.5.2.6.2 MAN_DAC[9:8], MAN_DAC[7:0]
          3. 9.5.2.6.3 DAC_TRIP_LOW
          4. 9.5.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
          5. 9.5.2.6.5 DAC_CLK_CNTR
          6. 9.5.2.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
          7. 9.5.2.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
        7. 9.5.2.7 (0x153 - 0x15F) PLL1 Configuration
          1. 9.5.2.7.1 CLKin0_R[9:8], CLKin0_R[7:0]
          2. 9.5.2.7.2 CLKin1_R[9:8], CLKin1_R[7:0]
          3. 9.5.2.7.3 CLKin2_R[9:8], CLKin2_R[7:0]
          4. 9.5.2.7.4 PLL1_N
          5. 9.5.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
          6. 9.5.2.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
          7. 9.5.2.7.7 PLL1_LD_MUX, PLL1_LD_TYPE
        8. 9.5.2.8 (0x160 - 0x16E) PLL2 Configuration
          1. 9.5.2.8.1 PLL2_R[4:0]
          2. 9.5.2.8.2 PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
          3. 9.5.2.8.3 PLL2_FCAL_DIS
          4. 9.5.2.8.4 PLL2_N
          5. 9.5.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
          6. 9.5.2.8.6 SYSREF_REQ_EN, PLL2_DLD_CNT
          7. 9.5.2.8.7 PLL2_LF_R4, PLL2_LF_R3
          8. 9.5.2.8.8 PLL2_LF_C4, PLL2_LF_C3
          9. 9.5.2.8.9 PLL2_LD_MUX, PLL2_LD_TYPE
        9. 9.5.2.9 (0x16F - 0x1FFF) Misc Registers
          1. 9.5.2.9.1  Fixed Register
          2. 9.5.2.9.2  Fixed Register
          3. 9.5.2.9.3  PLL2_PRE_PD, PLL2_PD
          4. 9.5.2.9.4  OPT_REG_1
          5. 9.5.2.9.5  OPT_REG_2
          6. 9.5.2.9.6  RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
          7. 9.5.2.9.7  RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
          8. 9.5.2.9.8  RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
          9. 9.5.2.9.9  RB_DAC_VALUE
          10. 9.5.2.9.10 RB_HOLDOVER
          11. 9.5.2.9.11 SPI_LOCK
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Digital Lock Detect Frequency Accuracy
        1. 10.1.1.1 Minimum Lock Time Calculation Example
      2. 10.1.2 Driving CLKin AND OSCin Inputs
        1. 10.1.2.1 Driving CLKin PINS With a Differential Source
        2. 10.1.2.2 Driving CLKin Pins With a Single-Ended Source
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Programming
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Pin Connection Recommendations
  11. 11Power Supply Recommendations
    1. 11.1 Current Consumption / Power Dissipation Calculations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Thermal Management
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TICS Pro
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

(3.15 V < VCC < 3.45 V, –40°C < TA < 85°C. Typical values at VCC = 3.3 V, TA = 25°C, at the Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC_PD Power-down supply current 1 3 mA
ICC_CLKS Supply current(2) 14 LVDS clocks enabled
PLL1 and PLL2 locked. 		485 mA
CLKin0/0*, CLKin1/1*, AND CLKin2/2* INPUT CLOCK SPECIFICATIONS
fCLKin Clock input frequency 0.001 400 MHz
SLEWCLKin Clock input slew rate(3) 20% to 80% 0.15 0.5 V/ns
VIDCLKin Clock input
differential input voltage(1)
Figure 2 		AC-coupled 0.125 1.55 |V|
VSSCLKin 0.25 3.1 Vpp
VCLKin Clock input
single-ended input voltage
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 0 (Bipolar)		 0.25 2.4 Vpp
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 1 (MOS)		 0.35 2.4
VCLKinX-offset| DC offset voltage between
CLKinX/CLKinX* (CLKinX* – CLKinX)		 Each pin AC-coupled, CLKin0/1/2
CLKinX_TYPE = 0 (Bipolar)		 0 |mV|
Each pin AC-coupled, CLKin0/1
CLKinX_TYPE = 1 (MOS)		 55
DC offset voltage between
CLKin2/CLKin2* (CLKin2* – CLKin2)		 Each pin AC-coupled
CLKinX_TYPE = 1 (MOS)		 20
VCLKin- VIH High input voltage DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
CLKinX_TYPE = 1 (MOS)		 2 VCC V
VCLKin- VIL Low input voltage 0 0.4 V
PLL1 SPECIFICATIONS
fPD1 PLL1 phase detector frequency 40 MHz
ICPout1SOURCE PLL1 charge
pump source current(4) 		VCPout1 = VCC/2, PLL1_CP_GAIN = 0 50 µA
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 150
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 250
… …
VCPout1 = VCC/2, PLL1_CP_GAIN = 14 1450
VCPout1 = VCC/2, PLL1_CP_GAIN = 15 1550
ICPout1SINK PLL1 charge
pump sink current(4) 		VCPout1=VCC/2, PLL1_CP_GAIN = 0 –50 µA
VCPout1=VCC/2, PLL1_CP_GAIN = 1 –150
VCPout1=VCC/2, PLL1_CP_GAIN = 2 –250
… …
VCPout1=VCC/2, PLL1_CP_GAIN = 14 –1450
VCPout1=VCC/2, PLL1_CP_GAIN = 15 –1550
ICPout1%MIS Charge pump
sink / source mismatch		 VCPout1 = VCC/2, T = 25 °C 1% 10%
ICPout1VTUNE Magnitude of charge pump current variation vs. charge pump voltage 0.5 V < VCPout1 < VCC – 0.5 V
TA = 25°C		 4%
ICPout1%TEMP Charge pump current vs. temperature variation 4%
ICPout1 TRI Charge pump TRI-STATE leakage current 0.5 V < VCPout < VCC – 0.5 V 5 nA
PN10kHz PLL 1/f noise at 10-kHz offset. Normalized to 1-GHz output frequency PLL1_CP_GAIN = 350 µA –117 dBc/Hz
PLL1_CP_GAIN = 1550 µA –118
PN1Hz Normalized phase noise contribution PLL1_CP_GAIN = 350 µA –221.5 dBc/Hz
PLL1_CP_GAIN = 1550 µA –223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin PLL2 reference input(6) 500 MHz
SLEWOSCin PLL2 reference clock minimum slew rate on OSCin (3) 20% to 80% 0.15 0.5 V/ns
VOSCin Input voltage for OSCin or OSCin*
AC-coupled; single-ended
(Unused pin AC-coupled to GND)		 0.2 2.4 Vpp
VIDOSCin Differential voltage swing
See Figure 2 		AC-coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
|VOSCin-offset| DC offset voltage between
OSCin/OSCin* (OSCinX* - OSCinX)		 Each pin AC-coupled 20 |mV|
fdoubler_max Doubler input frequency (5) EN_PLL2_REF_2X = 1(7);
OSCin duty cycle 40% to 60%		 155 MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
FXTAL Crystal frequency range Fundamental mode crystal
ESR = 200 Ω (10 to 30 MHz)
ESR = 125 Ω (30 to 40 MHz)		 10 40 MHz
CIN Input capacitance of OSCin port –40°C to +85°C 1 pF
PLL2 PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS
fPD2 Phase detector frequency (5) 155 MHz
ICPoutSOURCE PLL2 charge pump source current (4) VCPout2=VCC/2, PLL2_CP_GAIN = 0 100 µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 1600
ICPoutSINK PLL2 charge pump sink current (4) VCPout2=VCC/2, PLL2_CP_GAIN = 0 –100 µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 –400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 –1600
ICPout2%MIS Charge pump sink/source mismatch VCPout2=VCC/2, TA = 25°C 1% 10%
ICPout2VTUNE Magnitude of charge pump current vs. charge pump voltage variation 0.5 V < VCPout2 < VCC – 0.5 V
TA = 25°C		 4%
ICPout2%TEMP Charge pump current vs. temperature variation 4%
ICPout2TRI Charge pump leakage 0.5 V < VCPout2 < VCC – 0.5 V 10 nA
PN10kHz PLL 1/f noise at 10-kHz offset(8). Normalized to
1-GHz output frequency		 PLL2_CP_GAIN = 1600 µA –120 dBc/Hz
PN1Hz Normalized phase noise contribution(9) PLL2_CP_GAIN = 400 µA –222.5 dBc/Hz
PLL2_CP_GAIN = 1600 µA –224
INTERNAL VCO SPECIFICATIONS
fVCO LMK04228 VCO tuning range VCO0 2370 2630 MHz
VCO1 2920 3080
KVCO LMK04228 fine tuning sensitivity LMK04228 VCO0 at 2370 MHz(10) 17 MHz/V
LMK04228 VCO0 at 2630 MHz(10) 27
LMK04228 VCO1 at 2920 MHz(10) 17
LMK04228 VCO1 at 3080 MHz(10) 23
|ΔTCL| Allowable temperature drift for continuous lock(11) After programming for lock, no changes to output configuration are permitted to assure continuous lock 125 °C
NOISE FLOOR
L(f)CLKout LMK04228, VCO0, noise floor
20-MHz offset(12) 		245.76 MHz LVDS –156.3 dBc/Hz
LVPECL16 with 240 Ω –161.6
LVPECL20 with 240 Ω –162.5
L(f)CLKout LMK04228, VCO1, noise floor
20-MHz offset(12) 		245.76 MHz LVDS –155.7 dBc/Hz
LVPECL16 with 240 Ω –160.3
LVPECL20 with 240 Ω –161.1
CLKout CLOSED-LOOP PHASE NOISE SPECIFICATIONS A COMMERCIAL QUALITY VCXO(15)
L(f)CLKout LMK04228
VCO0
SSB phase noise(12)
245.76 MHz		 Offset = 1 kHz –115.2 dBc/Hz
Offset = 10 kHz –126.5
Offset = 100 kHz –128.3
Offset = 1 MHz –150.0
Offset = 10 MHz LVDS –157.9
LVPECL20 with 240 Ω –163.1
L(f)CLKout LMK04228
VCO1
SSB phase noise(12)
245.76 MHz		 Offset = 1 kHz –115.1 dBc/Hz
Offset = 10 kHz –126.3
Offset = 100 kHz –127.5
Offset = 1 MHz –154.4
Offset = 10 MHz LVDS –157.9
LVPECL20 with 240 Ω –162.3
CLKout CLOSED-LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO(15)
JCLKout LMK04228, VCO0
fCLKout = 245.76 MHz
Integrated RMS jitter (12) 		LVDS, BW = 100 Hz to 20 MHz 256 fs rms
LVDS, BW = 12 kHz to 20 MHz 183
LVPECL20 /w 240 Ω,
BW = 100 Hz to 20 MHz		 254
LVPECL20 /w 240 Ω,
BW = 12 kHz to 20 MHz		 176
LMK04228, VCO1
fCLKout = 245.76 MHz
Integrated RMS jitter (12) 		LVDS, BW = 100 Hz to 20 MHz 246
LVDS, BW = 12 kHz to 20 MHz 162
LVPECL16 with 240 Ω,
BW = 100 Hz to 20 MHz		 245
LVPECL20 with 240 Ω,
BW = 12 kHz to 20 MHz		 156
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
fCLKout-startup Default output clock frequency at device power on (16)(17) LMK04228 315 MHz
fOSCout OSCout frequency See(5) 500 MHz
CLOCK SKEW AND DELAY
|TSKEW| DCLKoutX to SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω
AC-coupled(13) 		Same pair, same format (14)
SDCLKoutY_MUX = 0 (device clock)		 25 |ps|
Maximum DCLKoutX or SDCLKoutY
to DCLKoutX or SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω
AC-coupled 		Any pair, same format (14)
SDCLKoutY_MUX = 0 (device clock)		 50
tsJESD204B SYSREF to device clock setup time base reference.
See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required.		 SDCLKoutY_MUX = 1 (SYSREF)
SYSREF_DIV = 30
SYSREF_DDLY = 8 (global)
SDCLKoutY_DDLY = 1 (2 cycles, local)
DCLKoutX_MUX = 1 (Div+DCC+HS)
DCLKoutX_DIV = 30
DCLKoutX_DDLY_CNTH = 7
DCLKoutX_DDLY_CNTL = 6
DCLKoutX_HS = 0
SDCLKoutY_HS = 0		 –80 ps
tPDCLKin0_
SDCLKout1		 Propagation delay from CLKin0 to SDCLKout1 CLKin0_OUT_MUX = 0 (SYSREF Mux)
SYSREF_CLKin0_MUX = 1 (CLKin0)
SDCLKout1_PD = 0
SDCLKout1_DDLY = 0 (Bypass)
SDCLKout1_MUX = 1 (SR)
EN_SYNC = 1
LVPECL16 with 240 Ω		 0.65 ns
fADLYmax Maximum analog delay frequency DCLKoutX_MUX = 4 1250 MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, AND OSCout)
VOD Differential output voltage T = 25°C, DC measurement
AC-coupled to receiver input
RL = 100-Ω differential termination		 395 |mV|
ΔVOD Change in magnitude of VOD for complementary output states –60 60 mV
VOS Output offset voltage 1.125 1.25 1.375 V
ΔVOS Change in VOS for complementary output states 35 |mV|
TR / TF Output rise time 20% to 80%, RL = 100 Ω, 245.76 MHz 180 ps
Output fall time 80% to 20%, RL = 100 Ω
ISA
ISB 		Output short-circuit current - single-ended Single-ended output shorted to GND
T = 25°C		 –24 24 mA
ISAB Output short-circuit current - differential Complementary outputs tied together –12 12 mA
LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
TR / TF 20% to 80% output rise RL = 100 Ω, emitter resistors = 240 Ω to GND
DCLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)		 150 ps
80% to 20% output fall time
1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH Output high voltage DC Measurement
Termination = 50 Ω to
VCC – 2 V		 VCC – 1.04 V
VOL Output low voltage VCC – 1.80 V
VOD Output voltage
See Figure 3 		760 |mV|
2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
VOH Output high voltage DC Measurement
Termination = 50 Ω to VCC – 2.3 V		 VCC – 1.09 V
VOL Output low voltage VCC – 2.05 V
VOD Output voltage
See Figure 3 		960 |mV|
LVCMOS CLOCK OUTPUTS (OSCout)
fCLKout Maximum frequency(18) 5-pF Load 250 MHz
VOH Output high voltage 1-mA Load VCC – 0.1 V
VOL Output low voltage 1-mA Load 0.1 V
IOH Output high current (source) VCC = 3.3 V, VO = 1.65 V 28 mA
IOL Output low current (sink) VCC = 3.3 V, VO = 1.65 V 28 mA
DUTYCLK Output duty cycle(20) VCC/2 to VCC/2,
FCLK = 100 MHz, T = 25°C		 50%
TR Output rise time 20% to 80%, RL = 50 Ω, CL = 5 pF 400 ps
TF Output fall time 80% to 20%, RL = 50 Ω, CL = 5 pF 400 ps
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, AND RESET/GPO)
VOH High-level output voltage IOH = –500 µA
CLKin_SELX_TYPE = 3 or 4
Status_LDX_TYPE = 3 or 4
RESET_TYPE = 3 or 4		 VCC – 0.4 V
VOL Low-level output voltage IOL = 500 µA
CLKin_SELX_TYPE = 3, 4, or 6
Status_LDX_TYPE = 3, 4, or 6
RESET_TYPE = 3, 4, or 6		 0.4 V
DIGITAL OUTPUT (SDIO)
VOH High-level output voltage IOH = –500 µA ; during SPI read.
SDIO_RDBK_TYPE = 0		 VCC – 0.4 V
VOL Low-level output voltage IOL = 500 µA ; during SPI read.
SDIO_RDBK_TYPE = 0 or 1		 0.4 V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, OR CS*)
VIH High-level input voltage 1.2 VCC V
VIL Low-level input voltage 0.4 V
DIGITAL INPUTS (CLKinX_SEL)
IIH High-level input current
VIH = VCC 		CLKin_SELX_TYPE = 0,
(high impedance)		 –5 5 µA
CLKin_SELX_TYPE = 1 (pullup) –5 5
CLKin_SELX_TYPE = 2 (pulldown) 10 80
IIL Low-level input current
VIL = 0 V		 CLKin_SELX_TYPE = 0,
(High Impedance)		 –5 5 µA
CLKin_SELX_TYPE = 1 (pullup) –40 –5
CLKin_SELX_TYPE = 2 (pulldown) –5 5
DIGITAL INPUT (RESET/GPO)
IIH High-level input current
VIH = VCC 		RESET_TYPE = 2
(pulldown)		 10 80 µA
IIL Low-level input current
VIL = 0 V		 RESET_TYPE = 0 (high impedance) –5 5 µA
RESET_TYPE = 1 (pullup) –40 -5
RESET_TYPE = 2 (pulldown) –5 5
DIGITAL INPUTS (SYNC)
IIH High-level input current VIH = VCC 25 µA
IIL Low-level input current VIL = 0 V –5 5
DIGITAL INPUTS (SCK, SDIO, CS*)
IIH High-level input current VIH = VCC –5 5 µA
IIL Low-level input current VIL = 0 –5 5 µA
DIGITAL INPUT TIMING
tHIGH RESET pin held high for device reset 25 ns
(1) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(2) See applications section Power Supply Recommendations for specific part configuration and how to calculate the ICC for a specific design.
(3) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common-mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
(4) This parameter is programmable
(5) Assured by characterization. ATE tested at 122.88 MHz.
(6) FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
(7) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
(8) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single-side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
(9) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) – 20log(N) – 10log(fPDX). LPLL_flat(f) is the single-side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(10) For frequencies in between, linearly interpolate to compute the typical Kvco
(11) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40°C to 85°C without violating specifications.
(12) Data collected using MACOM H-183-4 balun. Loop filter is C1 = 82 pF, C2 = 2.2 nF, R2 = 1800 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 650 µA, PLL2_CP = 1600 µA. VCO0 loop filter bandwidth = 176 kHz, phase margin = 67 degrees. VCO1 Loop filter loop bandwidth = 169 kHz, phase margin = 66 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.
(13) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
(14) LVPECL uses 120-Ω emitter resistor, LVDS uses 560-Ω shunt.
(15) VCXO used is a 30.72 MHz (TXC Bex05).
(16) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.
(17) Default outputs on DCLKout4, DCLKout6, DCLKout8, DCLKout10 and OSCout.
(18) Assured by characterization. ATE tested to 10 MHz.
(19) 20 MHz
(20) Assumes OSCin has 50% input duty cycle.