SNAS689A
October 2017 – July 2019
LMK04228
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Schematic
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
SPI Interface Timing
7.7
Timing Diagram
8
Parameter Measurement Information
8.1
Charge Pump Current Specification Definitions
8.1.1
Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
8.1.2
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
8.1.3
Charge Pump Output Current Magnitude Variation vs. Ambient Temperature
8.2
Differential Voltage Measurement Terminology
9
Detailed Description
9.1
Overview
9.1.1
Jitter Cleaning
9.1.2
JEDEC JESD204B Support
9.1.3
Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
9.1.4
VCXO- and Crystal-Buffered Output
9.1.5
Frequency Holdover
9.1.6
PLL2 Integrated Loop Filter Poles
9.1.7
Internal VCOs
9.1.8
Clock Distribution
9.1.8.1
Device Clock Divider
9.1.8.2
SYSREF Clock Divider
9.1.8.3
Device Clock Delay
9.1.8.4
SYSREF Delay
9.1.8.5
Programmable Output Formats
9.1.8.6
Clock Output Synchronization
9.1.9
Status Pins
9.2
Functional Block Diagrams
9.3
Feature Description
9.3.1
SYNC/SYSREF
9.3.2
JEDEC JESD204B
9.3.2.1
How to Enable SYSREF
9.3.2.1.1
Setup of SYSREF Example
9.3.2.1.2
SYSREF_CLR
9.3.2.2
SYSREF Modes
9.3.2.2.1
SYSREF Pulser
9.3.2.2.2
Continuous SYSREF
9.3.2.2.3
SYSREF Request
9.3.3
Digital Delay
9.3.3.1
Fixed Digital Delay
9.3.3.1.1
Fixed Digital Delay Example
9.3.4
SYSREF to Device Clock Alignment
9.3.5
Input Clock Switching
9.3.5.1
Input Clock Switching - Manual Mode
9.3.5.2
Input Clock Switching - Pin Select Mode
9.3.5.2.1
Configuring Pin Select Mode
9.3.5.3
Input Clock Switching - Automatic Mode
9.3.5.3.1
Starting Active Clock
9.3.6
Digital Lock Detect
9.3.6.1
Calculating Digital Lock Detect Frequency Accuracy
9.3.7
Holdover
9.3.7.1
Enable Holdover
9.3.7.1.1
Fixed (Manual) CPout1 Holdover Mode
9.3.7.1.2
Tracked CPout1 Holdover Mode
9.3.7.2
During Holdover
9.3.7.3
Exiting Holdover
9.3.7.4
Holdover Frequency Accuracy and DAC Performance
9.3.7.5
Holdover Mode - Automatic Exit of Holdover
9.4
Programming
9.4.1
Recommended Programming Sequence
9.4.1.1
SPI LOCK
9.4.1.2
SYSREF_CLR
9.5
Register Maps
9.5.1
Register Map for Device Programming
9.5.2
Device Register Descriptions
9.5.2.1
System Functions
9.5.2.1.1
RESET, SPI_3WIRE_DIS
9.5.2.1.2
POWERDOWN
9.5.2.1.3
ID_DEVICE_TYPE
9.5.2.1.4
ID_PROD[15:8], ID_PROD
9.5.2.1.5
ID_MASKREV
9.5.2.1.6
ID_VNDR[15:8], ID_VNDR
9.5.2.2
(0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
9.5.2.2.1
CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV
9.5.2.2.2
DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL
9.5.2.2.3
DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX
9.5.2.2.4
DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS
9.5.2.2.5
SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY
9.5.2.2.6
DCLKoutX_DDLY_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
9.5.2.2.7
SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT
9.5.2.3
SYSREF, SYNC, and Device Config
9.5.2.3.1
VCO_MUX, OSCout_FMT
9.5.2.3.2
SYSREF_CLKin0_MUX, SYSREF_MUX
9.5.2.3.3
SYSREF_DIV[12:8], SYSREF_DIV[7:0]
9.5.2.3.4
SYSREF_DDLY[12:8], SYSREF_DDLY[7:0]
9.5.2.3.5
SYSREF_PULSE_CNT
9.5.2.3.6
PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
9.5.2.3.7
SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
9.5.2.3.8
SYNC_DISSYSREF, SYNC_DISX
9.5.2.3.9
Fixed Register
9.5.2.4
(0x146 - 0x149) CLKin Control
9.5.2.4.1
CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
9.5.2.4.2
CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX
9.5.2.4.3
CLKin_SEL0_MUX, CLKin_SEL0_TYPE
9.5.2.4.4
SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
9.5.2.5
RESET_MUX, RESET_TYPE
9.5.2.6
(0x14B - 0x152) Holdover
9.5.2.6.1
LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
9.5.2.6.2
MAN_DAC[9:8], MAN_DAC[7:0]
9.5.2.6.3
DAC_TRIP_LOW
9.5.2.6.4
DAC_CLK_MULT, DAC_TRIP_HIGH
9.5.2.6.5
DAC_CLK_CNTR
9.5.2.6.6
CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
9.5.2.6.7
HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
9.5.2.7
(0x153 - 0x15F) PLL1 Configuration
9.5.2.7.1
CLKin0_R[9:8], CLKin0_R[7:0]
9.5.2.7.2
CLKin1_R[9:8], CLKin1_R[7:0]
9.5.2.7.3
CLKin2_R[9:8], CLKin2_R[7:0]
9.5.2.7.4
PLL1_N
9.5.2.7.5
PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
9.5.2.7.6
PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
9.5.2.7.7
PLL1_LD_MUX, PLL1_LD_TYPE
9.5.2.8
(0x160 - 0x16E) PLL2 Configuration
9.5.2.8.1
PLL2_R[4:0]
9.5.2.8.2
PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN
9.5.2.8.3
PLL2_FCAL_DIS
9.5.2.8.4
PLL2_N
9.5.2.8.5
PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
9.5.2.8.6
SYSREF_REQ_EN, PLL2_DLD_CNT
9.5.2.8.7
PLL2_LF_R4, PLL2_LF_R3
9.5.2.8.8
PLL2_LF_C4, PLL2_LF_C3
9.5.2.8.9
PLL2_LD_MUX, PLL2_LD_TYPE
9.5.2.9
(0x16F - 0x1FFF) Misc Registers
9.5.2.9.1
Fixed Register
9.5.2.9.2
Fixed Register
9.5.2.9.3
PLL2_PRE_PD, PLL2_PD
9.5.2.9.4
OPT_REG_1
9.5.2.9.5
OPT_REG_2
9.5.2.9.6
RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
9.5.2.9.7
RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
9.5.2.9.8
RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
9.5.2.9.9
RB_DAC_VALUE
9.5.2.9.10
RB_HOLDOVER
9.5.2.9.11
SPI_LOCK
10
Application and Implementation
10.1
Application Information
10.1.1
Digital Lock Detect Frequency Accuracy
10.1.1.1
Minimum Lock Time Calculation Example
10.1.2
Driving CLKin AND OSCin Inputs
10.1.2.1
Driving CLKin PINS With a Differential Source
10.1.2.2
Driving CLKin Pins With a Single-Ended Source
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Device Programming
10.3
Do's and Don'ts
10.3.1
Pin Connection Recommendations
11
Power Supply Recommendations
11.1
Current Consumption / Power Dissipation Calculations
12
Layout
12.1
Layout Guidelines
12.1.1
Thermal Management
12.2
Layout Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
TICS Pro
13.2
Community Resources
13.3
Trademarks
13.4
Electrostatic Discharge Caution
13.5
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
NKD|64
MPQS032B
Thermal pad, mechanical data (Package|Pins)
NKD|64
QFND765
Orderable Information
snas689a_oa
snas689a_pm
12.1
Layout Guidelines