The LMK04816 device is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual-loop PLLATINUM architecture enables 111-fs RMS jitter (12 kHz to
20 MHz) using a low-noise VCXO module or sub-200-fs RMS jitter (12 kHz to 20 MHz) using a low-cost external crystal and varactor diode.
The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LMK04816 | WQFN (64) | 9.00 mm × 9.00 mm |
Changes from B Revision (April 2013) to C Revision
Changes from A Revision (April 2013) to B Revision
PIN | I/O | TYPE | DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1, 2 | CLKout0, CLKout0* | O | Programmable | Clock output 0 (clock group 0) |
3, 4 | CLKout1*, CLKout1 | O | Programmable | Clock output 1 (clock group 0) |
6 | SYNC | I/O | Programmable | CLKout Synchronization input or programmable status pin |
Status_CLKin2 | I/O | Input for pin control of PLL1 reference clock selection. CLKin2 LOS status and other options available by programming. | ||
5, 7, 8, 9 | NC | — | — | No Connection. These pins must be left floating. |
10 | Vcc1 | — | PWR | Power supply for VCO LDO |
11 | LDObyp1 | — | ANLG | LDO Bypass, bypassed to ground with 10-µF capacitor |
12 | LDObyp2 | — | ANLG | LDO Bypass, bypassed to ground with a 0.1-µF capacitor |
13, 14 | CLKout2, CLKout2* | O | Programmable | Clock output 2 (clock group 1) |
15, 16 | CLKout3*, CLKout3 | O | Programmable | Clock output 3 (clock group 1) |
17 | Vcc2 | — | PWR | Power supply for clock group 1: CLKout2 and CLKout3 |
18 | Vcc3 | — | PWR | Power supply for clock group 2: CLKout4 and CLKout5 |
19, 20 | CLKout4, CLKout4* | O | Programmable | Clock output 4 (clock group 2) |
21, 22 | CLKout5*, CLKout5 | O | Programmable | Clock output 5 (clock group 2) |
23 | GND | — | PWR | Ground |
24 | Vcc4 | — | PWR | Power supply for digital |
25, 26 | CLKin1, CLKin1* | I | ANLG | Reference Clock Input Port 1 for PLL1. AC- or DC-Coupled |
FBCLKin, FBCLKin* | Feedback input for external clock feedback input (0-delay mode). AC- or DC-Coupled | |||
Fin, Fin* | External VCO input (External VCO mode). AC- or DC-Coupled | |||
27 | Status_Holdover | I/O | Programmable | Programmable status pin, default readback output. Programmable to holdover mode indicator. Other options available by programming. |
28, 29 | CLKin0, CLKin0* | I | ANLG | Reference Clock Input Port 0 for PLL1, AC- or DC-Coupled |
30 | Vcc5 | — | PWR | Power supply for clock inputs |
31, 32 | CLKin2, CLKin2* | I | ANLG | Reference Clock Input Port 2 for PLL1, AC- or DC-Coupled |
33 | Status_LD | I/O | Programmable | Programmable status pin, default lock detect for PLL1 and PLL2. Other options available by programming. |
34 | CPout1 | O | ANLG | Charge pump 1 output |
35 | Vcc6 | — | PWR | Power supply for PLL1, charge pump 1 |
36, 37 | OSCin, OSCin* | I | ANLG | Feedback to PLL1, Reference input to PLL2, AC-Coupled |
38 | Vcc7 | — | PWR | Power supply for OSCin port |
39, 40 | OSCout0, OSCout0* | O | Programmable | Buffered output 0 of OSCin port |
41 | Vcc8 | — | PWR | Power supply for PLL2, charge pump 2 |
42 | CPout2 | O | ANLG | Charge pump 2 output |
43 | Vcc9 | — | PWR | Power supply for PLL2 |
44 | LEuWire | I | CMOS | MICROWIRE Latch Enable Input |
45 | CLKuWire | I | CMOS | MICROWIRE Clock Input |
46 | DATAuWire | I | CMOS | MICROWIRE Data Input |
47 | Vcc10 | — | PWR | Power supply for clock group 3: CLKout6 and CLKout7 |
48, 49 | CLKout6, CLKout6* | O | Programmable | Clock output 6 (clock group 3) |
50, 51 | CLKout7*, CLKout7 | O | Programmable | Clock output 7 (clock group 3) |
52 | Vcc11 | — | PWR | Power supply for clock group 4: CLKout8 and CLKout9 |
53, 54 | CLKout8, CLKout8* | O | Programmable | Clock output 8 (clock group 4) |
55, 56 | CLKout9*, CLKout9 | O | Programmable | Clock output 9 (clock group 4) |
57 | Vcc12 | — | PWR | Power supply for clock group 5: CLKout10 and CLKout11 |
58, 59 | CLKout10, CLKout10* | O | Programmable | Clock output 10 (clock group 5) |
60, 61 | CLKout11*, CLKout11 | O | Programmable | Clock output 11 (clock group 5) |
62 | Status_CLKin0 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin0 LOS status and other options available by programming. |
63 | Status_CLKin1 | I/O | Programmable | Programmable status pin. Default is input for pin control of PLL1 reference clock selection. CLKin1 LOS status and other options available by programming. |
64 | Vcc13 | — | PWR | Power supply for clock group 0: CLKout0 and CLKout1 |
DAP | DAP | — | GND | DIE ATTACH PAD, connect to GND |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage (4) | –0.3 | 3.6 | V |
VIN | Input voltage | –0.3 | (VCC + 0.3) | V |
TL | Lead temperature (solder 4 seconds) | 260 | °C | |
TJ | Junction temperature | 150 | °C | |
IIN | Differential input current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) |
±5 | mA | |
MSL | Moisture sensitivity level | 3 | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±750 | |||
Machine model (MM) | ±150 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
TJ | Junction temperature | 125 | °C | |||
TA | Ambient temperature | VCC = 3.3 V | –40 | 25 | 85 | °C |
VCC | Supply voltage | 3.15 | 3.3 | 3.45 | V |
THERMAL METRIC(1) | LMK04816 | UNIT | |
---|---|---|---|
NKD (WQFN) | |||
64 PINS | |||
RθJA | Junction-to-ambient thermal resistance (2) | 24.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance (3) | 6.1 | °C/W |
RθJB | Junction-to-board thermal resistance (4) | 3.5 | °C/W |
ψJT | Junction-to-top characterization parameter (5) | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter (6) | 3.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance (7) | 0.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CURRENT CONSUMPTION | |||||||
ICC_PD | Power-down supply current | 1 | 3 | mA | |||
ICC_CLKS | Supply current with all clocks enabled (1) | All clock delays disabled, CLKoutX_Y_DIV = 1045, CLKoutX_TYPE = 1 (LVDS), PLL1 and PLL2 locked. |
505 | 590 | mA | ||
CLKin0/0*, CLKin1/1*, AND CLKin2/2* INPUT CLOCK SPECIFICATIONS | |||||||
fCLKin | Clock input frequency (2) | 0.001 | 500 | MHz | |||
SLEWCLKin | Clock input slew rate (3)(4) | 20% to 80% | 0.15 | 0.5 | V/ns | ||
VIDCLKin | Clock input Differential input voltage (5) Figure 5 |
AC-coupled CLKinX_BUF_TYPE = 0 (bipolar) |
0.25 | 1.55 | |V| | ||
VSSCLKin | 0.5 | 3.1 | Vpp | ||||
VIDCLKin | AC-coupled CLKinX_BUF_TYPE = 1 (MOS) |
0.25 | 1.55 | |V| | |||
VSSCLKin | 0.5 | 3.1 | Vpp | ||||
VCLKin | Clock input Single-ended input voltage (3) |
AC-coupled to CLKinX; CLKinX* AC-coupled to ground CLKinX_BUF_TYPE = 0 (bipolar) |
0.25 | 2.4 | Vpp | ||
AC-coupled to CLKinX; CLKinX* AC-coupled to ground CLKinX_BUF_TYPE = 1 (MOS) |
0.25 | 2.4 | Vpp | ||||
VCLKin0-offset | DC offset voltage between CLKin0/CLKin0* CLKin0* – CLKin0 |
Each pin AC-coupled CLKin0_BUF_TYPE = 0 (Bipolar) |
20 | mV | |||
VCLKin1-offset | DC offset voltage between CLKin1/CLKin1* CLKin1* – CLKin1 |
0 | mV | ||||
VCLKin2-offset | DC offset voltage between CLKin2/CLKin2* CLKin2* – CLKin2 |
20 | mV | ||||
VCLKinX-offset | DC offset voltage between CLKinX/CLKinX* CLKinX* – CLKinX |
Each pin AC-coupled CLKinX_BUF_TYPE = 1 (MOS) |
55 | mV | |||
VCLKin- VIH | High input voltage | DC-coupled to CLKinX; CLKinX* AC-coupled to ground CLKinX_BUF_TYPE = 1 (MOS) |
2.0 | VCC | V | ||
VCLKin- VIL | Low input voltage | 0 | 0.4 | V | |||
FBCLKin/FBCLKin* AND Fin/Fin* INPUT SPECIFICATIONS | |||||||
fFBCLKin | Clock input frequency (3) | AC-coupled (CLKinX_BUF_TYPE = 0) MODE = 2 or 8; FEEDBACK_MUX = 6 |
0.001 | 1000 | MHz | ||
fFin | Clock input frequency (3) | AC-coupled (CLKinX_BUF_TYPE = 0) MODE = 3 or 11 |
0.001 | 3100 | MHz | ||
VFBCLKin/Fin | Single-ended clock input voltage (3) | AC-coupled; (CLKinX_BUF_TYPE = 0) |
0.25 | 2 | Vpp | ||
SLEWFBCLKin/Fin | Slew rate on CLKin (3) | AC-coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0) |
0.15 | 0.5 | V/ns | ||
PLL1 SPECIFICATIONS | |||||||
fPD1 | PLL1 phase detector frequency | 40 | MHz | ||||
ICPout1SOURCE | PLL1 charge Pump source current (6) |
VCPout1 = VCC / 2, PLL1_CP_GAIN = 0 | 100 | µA | |||
VCPout1 = VCC / 2, PLL1_CP_GAIN = 1 | 200 | ||||||
VCPout1 = VCC / 2, PLL1_CP_GAIN = 2 | 400 | ||||||
VCPout1 = VCC / 2, PLL1_CP_GAIN = 3 | 1600 | ||||||
ICPout1SINK | PLL1 charge Pump sink current (6) |
VCPout1 = VCC / 2, PLL1_CP_GAIN = 0 | –100 | µA | |||
VCPout1 = VCC / 2, PLL1_CP_GAIN = 1 | –200 | ||||||
VCPout1 = VCC / 2, PLL1_CP_GAIN = 2 | –400 | ||||||
VCPout1 = VCC / 2, PLL1_CP_GAIN = 3 | –1600 | ||||||
ICPout1%MIS | Charge pump Sink / source mismatch |
VCPout1 = VCC / 2, T = 25°C | 3% | 10% | |||
ICPout1VTUNE | Magnitude of charge pump current variation vs. charge pump voltage | 0.5 V < VCPout1 < VCC – 0.5 V TA = 25°C |
4% | ||||
ICPout1%TEMP | Charge pump current vs. temperature variation | 4% | |||||
ICPout1 TRI | Charge pump tri-state leakage current | 0.5 V < VCPout < VCC – 0.5 V | 5 | nA | |||
PN10kHz | PLL 1/f noise at 10-kHz offset. Normalized to 1-GHz output frequency | PLL1_CP_GAIN = 400 µA | –117 | dBc/Hz | |||
PLL1_CP_GAIN = 1600 µA | –118 | ||||||
PN1Hz | Normalized phase noise contribution | PLL1_CP_GAIN = 400 µA | –221.5 | dBc/Hz | |||
PLL1_CP_GAIN = 1600 µA | –223 | ||||||
PLL2 REFERENCE INPUT (OSCIN) SPECIFICATIONS | |||||||
fOSCin | PLL2 reference input (7) | 500 | MHz | ||||
SLEWOSCin | PLL2 Reference Clock minimum slew rate on OSCin (3) | 20% to 80% | 0.15 | 0.5 | V/ns | ||
VOSCin | Input voltage for OSCin or OSCin* (3) | AC-coupled; single-ended (Unused pin AC-coupled to GND) | 0.2 | 2.4 | Vpp | ||
VIDOSCin | Differential voltage swing Figure 5 | AC-coupled | 0.2 | 1.55 | |V| | ||
VSSOSCin | 0.4 | 3.1 | Vpp | ||||
VOSCin-offset | DC offset voltage between OSCin/OSCin* OSCinX* – OSCinX |
Each pin AC-coupled | 20 | mV | |||
fdoubler_max | Doubler input frequency (3) | EN_PLL2_REF_2X = 1;(8)
OSCin Duty Cycle 40% to 60% |
155 | MHz | |||
CRYSTAL OSCILLATOR MODE SPECIFICATIONS | |||||||
fXTAL | Crystal frequency range (3) | RESR < 40 Ω | 6 | 20.5 | MHz | ||
PXTAL | Crystal power dissipation (9) | Vectron VXB1 crystal, 20.48 MHz, RESR < 40 Ω XTAL_LVL = 0 |
100 | µW | |||
CIN | Input capacitance of LMK04816 OSCin port | -40 to +85°C | 6 | pF | |||
PLL2 PHASE DETECTOR AND CHARGE-PUMP SPECIFICATIONS | |||||||
fPD2 | Phase detector frequency | 155 | MHz | ||||
ICPoutSOURCE | PLL2 charge pump source current (6) | VCPout2=VCC / 2, PLL2_CP_GAIN = 0 | 100 | µA | |||
VCPout2=VCC / 2, PLL2_CP_GAIN = 1 | 400 | ||||||
VCPout2=VCC / 2, PLL2_CP_GAIN = 2 | 1600 | ||||||
VCPout2=VCC / 2, PLL2_CP_GAIN = 3 | 3200 | ||||||
ICPoutSINK | PLL2 charge pump sink current (6) | VCPout2=VCC / 2, PLL2_CP_GAIN = 0 | –100 | µA | |||
VCPout2=VCC / 2, PLL2_CP_GAIN = 1 | –400 | ||||||
VCPout2=VCC / 2, PLL2_CP_GAIN = 2 | –1600 | ||||||
VCPout2=VCC / 2, PLL2_CP_GAIN = 3 | –3200 | ||||||
ICPout2%MIS | Charge pump sink and source mismatch | VCPout2=VCC / 2, TA = 25 °C | 3% | 10% | |||
ICPout2VTUNE | Magnitude of charge pump current vs. charge pump voltage variation | 0.5 V < VCPout2 < VCC – 0.5 V TA = 25°C |
4% | ||||
ICPout2%TEMP | Charge pump current vs. temperature variation | 4% | |||||
ICPout2TRI | Charge pump leakage | 0.5 V < VCPout2 < VCC – 0.5 V | 10 | nA | |||
PN10kHz | PLL 1/f noise at 10-kHz offset (10)
Normalized to 1-GHz output frequency |
PLL2_CP_GAIN = 400 µA | –118 | dBc/Hz | |||
PLL2_CP_GAIN = 3200 µA | –121 | ||||||
PN1Hz | Normalized phase noise contribution (11) | PLL2_CP_GAIN = 400 µA | –222.5 | dBc/Hz | |||
PLL2_CP_GAIN = 3200 µA | –227 | ||||||
INTERNAL VCO SPECIFICATIONS | |||||||
fVCO | VCO tuning range | LMK04816 | 2370 | 2600 | MHz | ||
KVCO | Fine tuning sensitivity | LMK04816 | lower end of the tuning range | 16 | MHz/V | ||
higher end of the tuning range | 21 | ||||||
|ΔTCL| | Allowable temperature drift for continuous lock (12) (3) | After programming R30 for lock, no changes to output configuration are permitted to ensure continuous lock | 125 | °C | |||
CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING A COMMERCIAL QUALITY VCXO(13) | |||||||
L(f)CLKout | LMK04816 fCLKout = 245.76 MHz SSB phase noise Measured at clock outputs Value is average for all output types (14) |
Offset = 1 kHz | –122.5 | dBc/Hz | |||
Offset = 10 kHz | –132.9 | ||||||
Offset = 100 kHz | –135.2 | ||||||
Offset = 800 kHz | –143.9 | ||||||
Offset = 10 MHz; LVDS | –156 | ||||||
Offset = 10 MHz; LVPECL 1600 mVpp | –157.5 | ||||||
Offset = 10 MHz; LVCMOS | –157.1 | ||||||
JCLKout
LVDS/LVPECL/LVCMOS |
LMK04816(14)
fCLKout = 245.76 MHz Integrated RMS jitter |
BW = 12 kHz to 20 MHz | 115 | fs rms | |||
BW = 100 Hz to 20 MHz | 123 | ||||||
CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW-NOISE CRYSTAL OSCILLATOR CIRCUIT(15) | |||||||
LMK04816 fCLKout = 245.76 MHz Integrated RMS jitter |
BW = 12 kHz to 20 MHz XTAL_LVL = 3 |
192 | fs rms | ||||
BW = 100 Hz to 20 MHz XTAL_LVL = 3 |
450 | ||||||
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY | |||||||
fCLKout-startup | Default output clock frequency at device power-on (16) | CLKout8, LVDS, LMK04816 | 90 | 98 | 110 | MHz | |
CLOCK SKEW AND DELAY | |||||||
|TSKEW| | Maximum CLKoutX to CLKoutY (17) (3) | LVDS-to-LVDS, T = 25°C, FCLK = 800 MHz, RL= 100 Ω AC coupled |
30 | ps | |||
LVPECL-to-LVPECL, T = 25°C, FCLK = 800 MHz, RL= 100 Ω emitter resistors = 240 Ω to GND AC coupled |
30 | ||||||
Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout (17) (3) | RL = 50 Ω, CL = 5 pF, T = 25°C, FCLK = 100 MHz. (17) |
100 | |||||
MixedTSKEW | LVDS or LVPECL to LVCMOS | Same device, T = 25 °C, 250 MHz |
750 | ps | |||
td0-DELAY | CLKin to CLKoutX delay (17) | MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0 |
1850 | ps | |||
MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0; VCO Frequency = 2457.6 MHz Analog delay select = 0; Feedback clock digital delay = 11; Feedback clock half step = 1; Output clock digital delay = 5; Output clock half step = 0; |
0 | ||||||
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1 | |||||||
fCLKout | Maximum frequency (3) (18) | RL = 100 Ω | 1536 | MHz | |||
VOD | Differential output voltage Figure 6 | T = 25°C, DC measurement AC-coupled to receiver input R = 100-Ω differential termination |
250 | 400 | 450 | |mV| | |
VSS | 500 | 800 | 900 | mVpp | |||
ΔVOD | Change in magnitude of VOD for complementary output states | –50 | 50 | mV | |||
VOS | Output offset voltage | 1.125 | 1.25 | 1.375 | V | ||
ΔVOS | Change in VOS for complementary output states | 35 | |mV| | ||||
TR / TF | Output rise time | 20% to 80%, RL = 100 Ω | 200 | ps | |||
Output fall time | 80% to 20%, RL = 100 Ω | ||||||
ISA
ISB |
Output short-circuit current - single-ended | Single-ended output shorted to GND, T = 25°C | –24 | 24 | mA | ||
ISAB | Output short-circuit current - differential | Complimentary outputs tied together | –12 | 12 | mA | ||
LVPECL CLOCK OUTPUTS (CLKoutX) | |||||||
fCLKout | Maximum frequency (3) (18) | 1536 | MHz | ||||
TR / TF | 20% to 80% output rise | RL = 100-Ω, emitter resistors = 240 Ω to GND CLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp) |
150 | ps | |||
80% to 20% output fall time | |||||||
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2 | |||||||
VOH | Output high voltage | T = 25°C, DC measurement Termination = 50 Ω to VCC - 1.4 V |
VCC – 1.03 | V | |||
VOL | Output low voltage | VCC – 1.41 | V | ||||
VOD | Output voltage Figure 6 | 305 | 380 | 440 | [mV] | ||
VSS | 610 | 760 | 880 | mVpp | |||
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3 | |||||||
VOH | Output high voltage | T = 25°C, DC measurement Termination = 50 Ω to VCC - 1.7 V |
VCC – 1.07 | V | |||
VOL | Output low voltage | VCC – 1.69 | V | ||||
VOD | Output voltage Figure 6 | 545 | 625 | 705 | |mV| | ||
VSS | 1090 | 1250 | 1410 | mVpp | |||
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4 | |||||||
VOH | Output high voltage | T = 25°C, DC Measurement Termination = 50 Ω to VCC - 2.0 V |
VCC – 1.1 | V | |||
VOL | Output low voltage | VCC – 1.97 | V | ||||
VOD | Output voltage Figure 6 | 660 | 870 | 965 | |mV| | ||
VSS | 1320 | 1740 | 1930 | mVpp | |||
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5 | |||||||
VOH | Output high voltage | T = 25°C, DC Measurement Termination = 50 Ω to VCC – 2.3 V |
VCC – 1.13 | V | |||
VOL | Output low voltage | VCC – 2.2 | V | ||||
VOD | Output voltage Figure 6 | 800 | 1070 | 1200 | |mV| | ||
VSS | 1600 | 2140 | 2400 | mVpp | |||
LVCMOS CLOCK OUTPUTS (CLKoutX) | |||||||
fCLKout | Maximum frequency (3) (18) | 5-pF Load | 250 | MHz | |||
VOH | Output high voltage | 1-mA Load | VCC – 0.1 | V | |||
VOL | Output low voltage | 1-mA Load | 0.1 | V | |||
IOH | Output high current (source) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | |||
IOL | Output low current (sink) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | |||
DUTYCLK | Output duty cycle (3) | VCC / 2 to VCC / 2, FCLK = 100 MHz, T = 25°C | 45% | 50% | 55% | ||
TR | Output rise time | 20% to 80%, RL = 50 Ω, CL = 5 pF |
400 | ps | |||
TF | Output fall time | 80% to 20%, RL = 50 Ω, CL = 5 pF |
400 | ps | |||
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC) | |||||||
VOH | High-level output voltage | IOH = –500 µA | VCC – 0.4 | V | |||
VOL | Low-level output voltage | IOL = 500 µA | 0.4 | V | |||
DIGITAL INPUTS (Status_CLKinX, SYNC) | |||||||
VIH | High-level input voltage | 1.6 | VCC | V | |||
VIL | Low-level input voltage | 0.4 | V | ||||
IIH | High-level input current VIH = VCC |
Status_CLKinX_TYPE = 0 (High impedance) |
–5 | 5 | µA | ||
Status_CLKinX_TYPE = 1 (Pullup) |
–5 | 5 | |||||
Status_CLKinX_TYPE = 2 (Pulldown) |
10 | 80 | |||||
IIL | Low-level input current VIL = 0 V |
Status_CLKinX_TYPE = 0 (High impedance) |
–5 | 5 | µA | ||
Status_CLKinX_TYPE = 1 (Pullup) |
–40 | -5 | |||||
Status_CLKinX_TYPE = 2 (Pulldown) |
–5 | 5 | |||||
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire) | |||||||
VIH | High-level input voltage | 1.6 | VCC | V | |||
VIL | Low-level input voltage | 0.4 | V | ||||
IIH | High-level input current | VIH = VCC | 5 | 25 | µA | ||
IIL | Low-level input current | VIL = 0 | –5 | 5 | µA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
TECS | LE-to-clock setup time | 25 | ns | ||
TDCS | Data-to-clock setup time | 25 | ns | ||
TCDH | Clock-to-data hold time | 8 | ns | ||
TCWH | Clock pulse width high | 25 | ns | ||
TCWL | Clock pulse width low | 25 | ns | ||
TCES | Clock-to-LE setup time | 25 | ns | ||
TEWH | LE pulse width | 25 | ns | ||
TCR | Falling clock to readback time | 25 | ns |
I1 = Charge-Pump Sink Current at VCPout = VCC – ΔV
I2 = Charge-Pump Sink Current at VCPout = VCC / 2
I3 = Charge-Pump Sink Current at VCPout = ΔV
I4 = Charge-Pump Source Current at VCPout = VCC – ΔV
I5 = Charge-Pump Source Current at VCPout = VCC / 2
I6 = Charge-Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
Use Equation 1 to calculate the charge-pump output current variation versus the charge-pump output voltage.
Use Equation 2 to calculate the charge-pump sink current versus the source current mismatch.
Use Equation 3 to calculate the charge-pump output current magnitude variation versus the temperature.
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading data sheets or communicating with other engineers. This section addresses the measurement and description of a differential signal so that the reader can understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.
Figure 5 shows the two different definitions side-by-side for inputs and Figure 6 shows the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
Refer to AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for more information.