SNAS698C May   2020  – November 2022 LMK04832-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Differences Between LMK04832-SP and LMK04832
        1. 8.1.1.1 Jitter Cleaning
        2. 8.1.1.2 JEDEC JESD204B Support
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 Inputs for PLL1
        2. 8.1.2.2 Inputs for PLL2
        3. 8.1.2.3 Inputs When Using Clock Distribution Mode
      3. 8.1.3 PLL1
        1. 8.1.3.1 Frequency Holdover
        2. 8.1.3.2 External VCXO for PLL1
      4. 8.1.4 PLL2
        1. 8.1.4.1 Internal VCOs for PLL2
        2. 8.1.4.2 External VCO Mode
      5. 8.1.5 Clock Distribution
        1. 8.1.5.1 Clock Divider
        2. 8.1.5.2 High Performance Divider Bypass Mode
        3. 8.1.5.3 SYSREF Clock Divider
        4. 8.1.5.4 Device Clock Delay
        5. 8.1.5.5 Dynamic Digital Delay
        6. 8.1.5.6 SYSREF Delay: Global and Local
        7. 8.1.5.7 Programmable Output Formats
        8. 8.1.5.8 Clock Output Synchronization
      6. 8.1.6 0-Delay
      7. 8.1.7 Status Pins
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Synchronizing PLL R Dividers
        1. 8.3.1.1 PLL1 R Divider Synchronization
        2. 8.3.1.2 PLL2 R Divider Synchronization
      2. 8.3.2 SYNC/SYSREF
      3. 8.3.3 JEDEC JESD204B
        1. 8.3.3.1 How to Enable SYSREF
          1. 8.3.3.1.1 Setup of SYSREF Example
          2. 8.3.3.1.2 SYSREF_CLR
        2. 8.3.3.2 SYSREF Modes
          1. 8.3.3.2.1 SYSREF Pulser
          2. 8.3.3.2.2 Continuous SYSREF
          3. 8.3.3.2.3 SYSREF Request
      4. 8.3.4 Digital Delay
        1. 8.3.4.1 Fixed Digital Delay
          1. 8.3.4.1.1 Fixed Digital Delay Example
        2. 8.3.4.2 Dynamic Digital Delay
        3. 8.3.4.3 Single and Multiple Dynamic Digital Delay Example
      5. 8.3.5 SYSREF to Device Clock Alignment
      6. 8.3.6 Input Clock Switching
        1. 8.3.6.1 Input Clock Switching - Manual Mode
        2. 8.3.6.2 Input Clock Switching - Pin Select Mode
        3. 8.3.6.3 Input Clock Switching - Automatic Mode
      7. 8.3.7 Digital Lock Detect
        1. 8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy
      8. 8.3.8 Holdover
        1. 8.3.8.1 Enable Holdover
          1. 8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode
          2. 8.3.8.1.2 Tracked CPout1 Holdover Mode
        2. 8.3.8.2 During Holdover
        3. 8.3.8.3 Exiting Holdover
        4. 8.3.8.4 Holdover Frequency Accuracy and DAC Performance
      9. 8.3.9 PLL2 Loop Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 DUAL PLL
        1. 8.4.1.1 Dual Loop
        2. 8.4.1.2 Dual Loop With Cascaded 0-Delay
        3. 8.4.1.3 Dual Loop With Nested 0-Delay
      2. 8.4.2 Single PLL
        1. 8.4.2.1 PLL2 Single Loop
        2. 8.4.2.2 PLL2 With External VCO
      3. 8.4.3 Distribution Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Sequence
    6. 8.6 Register Maps
      1. 8.6.1 Register Map for Device Programming
      2. 8.6.2 Device Register Descriptions
        1. 8.6.2.1 System Functions
          1. 8.6.2.1.1 RESET, SPI_3WIRE_DIS
          2. 8.6.2.1.2 POWERDOWN
          3. 8.6.2.1.3 ID_DEVICE_TYPE
          4. 8.6.2.1.4 ID_PROD
          5. 8.6.2.1.5 ID_MASKREV
          6. 8.6.2.1.6 ID_VNDR
        2. 8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls
          1. 8.6.2.2.1 DCLKX_Y_DIV
          2. 8.6.2.2.2 DCLKX_Y_DDLY
          3. 8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8], DCLKX_Y_DIV[9:8]
          4. 8.6.2.2.4 CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS
          5. 8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS
          6. 8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY
          7. 8.6.2.2.7 SCLKX_Y_DDLY
          8. 8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT
        3. 8.6.2.3 SYSREF, SYNC, and Device Config
          1. 8.6.2.3.1  VCO_MUX, OSCout_MUX, OSCout_FMT
          2. 8.6.2.3.2  SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX
          3. 8.6.2.3.3  SYSREF_DIV
          4. 8.6.2.3.4  SYSREF_DDLY
          5. 8.6.2.3.5  SYSREF_PULSE_CNT
          6. 8.6.2.3.6  PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN
          7. 8.6.2.3.7  PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD
          8. 8.6.2.3.8  DDLYdSYSREF_EN, DDLYdX_EN
          9. 8.6.2.3.9  DDLYd_STEP_CNT
          10. 8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE
          11. 8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX
          12. 8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN, FIN0_DIV2_EN, FIN0_INPUT_TYPE
        4. 8.6.2.4 (0x146 - 0x149) CLKin Control
          1. 8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE
          2. 8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX, CLKin0_DEMUX
          3. 8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE
          4. 8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
        5. 8.6.2.5 RESET_MUX, RESET_TYPE
        6. 8.6.2.6 (0x14B - 0x152) Holdover
          1. 8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]
          2. 8.6.2.6.2 MAN_DAC
          3. 8.6.2.6.3 DAC_TRIP_LOW
          4. 8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH
          5. 8.6.2.6.5 DAC_CLK_CNTR
          6. 8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT, HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN
          7. 8.6.2.6.7 HOLDOVER_DLD_CNT
        7. 8.6.2.7 (0x153 - 0x15F) PLL1 Configuration
          1. 8.6.2.7.1 CLKin0_R
          2. 8.6.2.7.2 CLKin1_R
          3. 8.6.2.7.3 CLKin2_R
          4. 8.6.2.7.4 PLL1_N
          5. 8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
          6. 8.6.2.7.6 PLL1_DLD_CNT
          7. 8.6.2.7.7 HOLDOVER_EXIT_NADJ
          8. 8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE
        8. 8.6.2.8 (0x160 - 0x16E) PLL2 Configuration
          1. 8.6.2.8.1 PLL2_R
          2. 8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN
          3. 8.6.2.8.3 PLL2_N_CAL
          4. 8.6.2.8.4 PLL2_N
          5. 8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI
          6. 8.6.2.8.6 PLL2_DLD_CNT
          7. 8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE
        9. 8.6.2.9 (0x16F - 0x555) Misc Registers
          1. 8.6.2.9.1 PLL2_PRE_PD, PLL2_PD, FIN0_PD
          2. 8.6.2.9.2 PLL1R_RST
          3. 8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST
          4. 8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD
          5. 8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS
          6. 8.6.2.9.6 RB_DAC_VALUE
          7. 8.6.2.9.7 RB_HOLDOVER
          8. 8.6.2.9.8 SPI_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Treatment of Unused Pins
      2. 9.1.2 Digital Lock Detect Frequency Accuracy
        1. 9.1.2.1 Minimum Lock Time Calculation Example
      3. 9.1.3 Driving CLKin AND OSCin Inputs
        1. 9.1.3.1 Driving CLKin and OSCin PINS With a Differential Source
        2. 9.1.3.2 Driving CLKin Pins With a Single-Ended Source
      4. 9.1.4 OSCin Doubler for Best Phase Noise Performance
      5. 9.1.5 Radiation Environments
        1. 9.1.5.1 Total Ionizing Dose
        2. 9.1.5.2 Single Event Effect
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
        2. 9.2.2.2 Device Configuration and Simulation
        3. 9.2.2.3 Device Programming
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Cold Sparing Considerations
        1. 9.3.1.1 Damage Prevention Details to Unpowered Device
      2. 9.3.2 Current Consumption
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Management
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Clock Architect
        2. 10.1.1.2 PLLatinum Sim
        3. 10.1.1.3 TICS Pro
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VDD, VDD_A = 3.3 V ± 5 %, –55 °C ≤TA ≤ 125 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise noted)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption
ICC Power Down Supply Current Device Powered Down 3.3 5 mA
Supply Current(1) PLL1 locked to external VCXO and PLL2 locked to internal VCO 4 CML 32 mA clocks in bypass
3 LVDS clock /12
4 SYSREF as LCPECL
3 SYSREF as LVDS		 1010
4 CML 32 mA clocks in bypass
3 LVDS clock /12
4 SYSREF as LCPECL (low state)
3 SYSREF as LVDS (low state)		 780
4 CML 32 mA clocks in bypass
3 LVDS clock /12
7 SYSREF outputs powered down		 675
CLKin Specifications
fCLKinX LOS Circuitry LOS_EN = 1 0.001 125 MHz
PLL1 CLKinX-TYPE=1(MOS) AC Coupled Input 0.001 250
CLKinX-TYPE=0 (Bipolar) AC Coupled Input 0.001 750
PLL2 CLKinX_TYPE=0 (Bipolar) AC Coupled Input 0.001 500
0-delay 0-delay with external feedback (CLKin1) AC Coupled Input 0.001 750
Distribution Mode CLKin1/Fin1 Pin only AC Coupled Input 0.001 3250
SLEWCLKin Input Slew Rate(2) 0.15 0.5 V/ns
VCLKinX/Fin1 Single-ended clock input voltage Input pin AC coupled; complementary pin AC coupled to GND 0.5 2.4 Vpp
VIDCLKinX/Fin1 Differential clock input voltage(3) AC coupled 0.125 1.55 |V|
VSSCLKinX/Fin1 0.25 3.1 Vpp
|VCLKinX-offset| DC offset voltage between CLKinX /CLKinX* Each Pin AC Coupled CLKin0/1/2 (Bipolar) 0 |mV|
CLKin0/1 (MOS) 55
CLKin2 (MOS) 20
VCLKinVIH High Input Voltage VCLKin-VIH DC Coupled Input 2 Vcc V
VCLKinVIL Low Input Voltage VCLKin-VIL DC Coupled Input 0 0.4 V
Fin0 Input Pin
fFin0 External Input Frequency AC Coupled Slew Rate > 150 V/us FIN0_DIV2_EN=1 1 3250 MHz
fFin0 FIN0_DIV2_EN=2 1 6400 MHz
VIDFin0 Differential Input Voltage AC Coupled 0.125 1.55 Vpp
VSSFin0 0.25 3.1 Vpp
PLL 1 Specifications
fPD1 Phase Detector Frequency 40 MHz
PN10kHz PLL Normalized 1/f Noise(4) PLL1_CP_GAIN = 350 µA –117 dBc/Hz
PLL1_CP_GAIN = 1550 µA –118
PN FOM PLL Figure of Merit(5) PLL1_CP_GAIN = 350 µA –221.5
PLL1_CP_GAIN = 1550 µA –223
ICPOUT1 Charge Pump Current(6) VCPout=Vcc/2 (note to tell customer that part works for 0-15) PLL1_CP_GAIN=0 50 µA
PLL1_CP_GAIN=1 150
PLL1_CP_GAIN=2 250
PLL1_CP_GAIN=4 450
PLL1_CP_GAIN=8 850
ICPout1%MIS Charge Pump Sink / Source Mismatch VCPout1 = Vcc/2, T = 25 °C VCPout1 = Vcc/2, T = 25 °C 1 10 %
ICPout1VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 4 10 %
ICPout1%TEMP Charge Pump Current vs. Temperature Varation 4 10 %
ICPOUT1TRI Charge Pump TRI_STATE Leakage Current 10 nA
OSCin Input
fOSCin EN_PLL2_REF_2X=0 0.001 500 MHz
EN_PLL2_REF_2X=1 0.001 320
SLEWOSCin Input Slew Rate 0.15 0.5 V/ns
VOSCin Input voltage for OSCin or OSCin* AC coupled; single-ended; unused pin AC coupled to GND 0.2 2.4 Vpp
VIDOSCin Differential voltage swing(3) AC coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
VCLKinXOffset DC offset voltage between CLKinX /CLKinX* Each Pin AC Coupled 20 mV
PLL 2 Specifications
fPD Phase Detector Frequency 320 MHz
PN10kHz PLL Normalized 1/f Noise(4) PLL2_CP_GAIN = 1600 uA –123 dBc/Hz
PLL2_CP_GAIN = 3200 uA -128
PN FOM PLL Figure of Merit(5) PLL2_CP_GAIN = 1600 uA –226.5
PLL2_CP_GAIN = 3200 uA -230
ICPOUT Charge Pump Current Magnitude(6) VCPout=Vcc/2 PLL2_CP_GAIN=2 1600 µA
PLL2_CP_GAIN=3 3200
ICPout1%MIS Charge Pump Sink / Source Mismatch VCPout1 = Vcc/2, T = 25 °C VCPout1 = Vcc/2, T = 25 °C 1 10 %
ICPout1VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 4 10 %
ICPout1%TEMP Charge Pump Current vs. Temperature Varation 4 10 %
ICPOUT1TRI Charge Pump TRI_STATE Leakage Current 10 nA
Internal VCO Specifications
fVCO VCO Frequency Range VCO0 2440 MHz
VCO1 3255
KVCO VCO Tuning Sensitivity VCO0 8 to 11 MHz/V
VCO1 17 to 23
|ΔTCL| Allowable temperature Drift for Continous Lock(7) VCO0 150 oC
Allowable temperature Drift for Continous Lock(7) VCO1 180 oC
L(f)VCO Open Loop VCO Phase Noise VCO0 at 2500 MHz 10 kHz -88.4 dBc/Hz
100 kHz -117
800 kHz -137.5
1 MHz -139.7
10 MHz -152.6
VCO0 at 2590 MHz 10 kHz -85.7
100 kHz -115.8
800 kHz -137
1 MHz -138.6
10 MHz -151.8
L(f)VCO Open Loop VCO Phase Noise VCO1 at 2700 MHz 10 kHz -82.6 dBc/Hz
100 kHz -112.3
800 kHz -134.9
1 MHz -137.2
10 MHz -151.1
VCO1 at 3200 MHz 10 kHz -81
100 kHz -110.4
800 kHz -134.3
1 MHz -135.6
10 MHz -149.3
Output Clock Skew and Timing
SKEWCLKinX Output to Output Skew Same Pair of Device clocks and same format 50 ps
Even to Even or Odd to Odd, Same Format 50
Even clock to Odd Clock 50
Additive Jitter in Distribution Mode from Fin Pin (note 6)
L(f)CLKout Additive jitter, Distribution mode with no divide 245.76 MHz Output Frequency, 12k-20MHz integration bandwidth LVCMOS 50 fs
LVDS 50
LVPECL 40
LCPECL 35
HSDS 40
CML 35
LVCMOS Outputs
f)CLKout Frequency 5 pF Load 250 MHz
L(f)CLKout Noise Floor 245.76 MHz 20 MHz Offset –160 dBc/Hz
VOH Output High Voltage 1 mA load Vcc–0.1 V
VOL Output Low Voltage 1 mA load 0.1 V
IOH Output High Current FD=1.65V –28 mA
IOL Output Low Current Vd=1.65V 28 mA
DUTY Output Duty Cycle 50 %
LVDS Clock Outputs
L(f)CLKout Noise Floor 245.76 MHz output 20 MHz Offset –159.5 dBc/Hz
TR/TF 20% to 80% Rise/Fall Time 175 ps
VOD Differential Output Voltage DC Measurement, AC coupled to receiver input RL = 100 Ω differential 400 mV
ΔVOD Change in VOD for complimentary output states –60 60 mV
VOS Output Offset Voltage 1.125 1.25 1.375 V
ΔVOS Change on VOS for complimentary Output states 35 mV
ISAISB Short circuit Output Current –24 24 mA
LCPECL Clock Outputs
L(f)CLKout Noise Floor 245.76 MHz output 20 MHz Offset –162.5 dBc/Hz
TR/TF 20% to 80% Rise/Fall Time 135 ps
VOH Output High Voltage DC Measurement with 50-Ω to 0.5V 1.4 V
VOL Output Low Voltage 0.6 V
VOD Differential Output Voltage DC Measurement with 50-Ω to 0.5V 870 mV
LVPECL Clock Outputs
L(f)CLKout Noise Floor 245.76 MHz output, LVPECL 2.0 V 20 MHz Offset –163 dBc/Hz
TR/TF 20% to 80% Rise/Fall Time 135 ps
VOH Output High Voltage DC Measurement termination 50 Ω to Vcc-2 V LVPECL 1.6 V Vcc-1 V
LVPECL 2.0 V Vcc-1
VOL Output Low Voltage LVPECL 1.6 V Vcc–1.8 V
LVPECL 2.0 V Vcc–2
VOD Differential Output Voltage 2.5 GHz, Em = 120 Ω to GND, RL = AC coupled 100  Ω LVPECL 1.6 V 0.8 V
LVPECL 2.0 V 1
HSDS Clock Outputs
L(f)CLKout Noise Floor 245.76 MHz output 20 MHz Offset –162 dBc/Hz
TR/TF 20% to 80% Rise/Fall Time 170 ps
VOH Output High Voltage DC Measurement with 50 Ω to 0.5V HSDS 6 mA Vcc–0.9 V
HSDS 8 mA Vcc–0.95
VOL Output Low Voltage HSDS 6 mA Vcc–1.5 V
HSDS 8 mA Vcc–1.7
VOD Output Voltage DC Measurement with 50 Ω to 0.5V HSDS 6 mA 0.6 V
HSDS 8 mA 0.75
ΔVOD Change on VOS for complimentary Output states HSDS 6 mA –80 80 mV
HSDS 8 mA –115 115
CML Outputs
L(f)CLKout Noise Floor 20 MHz Offset –163 dBc/Hz
TR/TF 20% to 80% Rise/Fall Time CML 16 mA 120 ps
CML 24 mA 125
CML 32 mA 135
VOH Output High Voltage 50 Ω pull up to Vcc, DC Measurement Vcc V
VOL Output Low Voltage 50 Ω pull up to Vcc, DC Measurement CML 16 mA Vcc–0.84 V
CML 24 mA Vcc–1.26
CML 32 mA Vcc–1.66
VOD Output Voltage 50 Ω pull up to Vcc, DC Measurement CML 16 mA 840 mV
CML 24 mA 1260
CML 32 mA 1660
50 Ω pull up to Vcc, DC Measurement, RL = AC coupled 100 Ω, 250 MHz CML 16 mA 550 mV
CML 24 mA 815
CML 32 mA 1070
Digital Outputs (CLKin_SELX,STATUS_LDX, and RESET/GPO,SDIO)
VOH Output High Voltage Vcc–0.4 V
VOL Output Low Voltage 0.4 V
Digital Inputs
VIH High-level input voltage 1.2 V
VIL Low-level input voltage 0.5 V
IIH High-level input current CLKinX_SEL,RESET/GPO,SYNC,SCK,SDIO, CS* 10 80 uA
SYNC VIH = VCC 25
IIL Low-level input current CLKinX_SEL,RESET/GPO,SYNC,SCK,SDIO, CS* –5 5 uA
IIL Low-level input current SYNC VIL = 0 V –5 5
(1) Use the TICS Pro tool to calculate Icc for a specific configuration
(2) Device will function with slew rate as low as 0.15 V/ns, however a slew rate of 0.5 V/ns or higher is recommended to get the best phase noise performance.
(3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(4) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10 kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10 kHz = LPLL_flicker(10 kHz) - 20 log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low-power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f)
(5) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1 HZ = LPLL_flat(f) - 20 log(N) - 10 log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(6) This parameter is programmable to more states than are shown in the electrical specifications
(7) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock.  This parameter is indirectly tested.