SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The DPLL supports locking to an input clock that has missing periods and is referred to as a gapped clock. Gapping severely increases the jitter of a clock, so the DPLL provides the high input jitter tolerance and low loop bandwidth necessary to generate a low-jitter periodic output clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. The gapped clock width cannot be longer than the reference clock period after the R divider (RPRI/SECREF / fPRI/SECREF). The reference input monitors should be configured to avoid any flags due to the worst-case clock gapping scenario to achieve and maintain lock. Reference switchover between two gapped clock inputs may violate the hitless switching specification if the switch occurs during a gap in either input clock.