SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The output clock distribution blocks shown in Figure 45 include six output muxes, six output dividers, and eight programmable output drivers. The output dividers support output synchronization (SYNC) to allow phase synchronization between two or more output channels. Also, the OUT7 channel has an optional zero-delay mode (ZDM) synchronization feature to support deterministic input-to-output phase alignment (typically for 1-PPS clocks) with programmable offset.