SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE(1) | DESCRIPTION | ||||||
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NAME | NO. | |||||||
POWER | ||||||||
GND | PAD | G | Ground / Thermal Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance. A 5×5 via pattern is recommended to connect the IC ground pad to the PCB ground layers. |
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VDD_IN | 5 | P | Core Supply (3.3 V) for Primary and Secondary Reference Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin. |
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VDD_XO | 33 | P | Core Supply (3.3 V) for XO Input.
Place a nearby 0.1-µF bypass capacitor on each pin. |
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VDD_PLL1 | 27 | P | Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin. |
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VDD_PLL2 | 36 | P | ||||||
VDD_DIG | 4 | P | ||||||
VDDO_01 | 18 | P | Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.
Place a nearby 0.1-µF bypass capacitor on each pin. |
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VDDO_23 | 19 | P | ||||||
VDDO_4 | 37 | P | ||||||
VDDO_5 | 40 | P | ||||||
VDDO_6 | 43 | P | ||||||
VDDO_7 | 46 | P | ||||||
CORE BLOCKS | ||||||||
LF1 | 29 | A | External Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby capacitor on each pin. For LF1, 0.47-µF is suggested for typical APLL1 loop bandwidths around 2.5 kHz. For LF2, 0.1-µF is suggested for typical APLL2 loop bandwidth around 500 kHz. |
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LF2 | 34 | A | ||||||
CAP_PLL1 | 28 | A | External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin. |
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CAP_PLL2 | 35 | A | ||||||
CAP_DIG | 3 | A | ||||||
INPUT BLOCKS | ||||||||
PRIREF_P | 6 | I | DPLL Primary and Secondary Reference Clock Inputs.
Each input pair can accept a differential or single-ended clock as a reference to the DPLL. Each pair has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground. An unused input pair can be left floating. |
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PRIREF_N | 7 | I | ||||||
SECREF_P | 10 | I | ||||||
SECREF_N | 11 | I | ||||||
XO_P | 31 | I | XO/TCXO/OCXO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator as a reference to the APLLs. This input has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to the P input with the N input pulled down to ground. A low-frequency TCXO or OCXO can be used to set the clock output frequency accuracy and stability during free-run and holdover modes. In DPLL mode, the XO frequency must have a non-integer relationship to the VCO1 frequency so APLL1 can operate in fractional mode (required for proper DPLL operation). In APLL-only mode, the XO frequency can have either an integer or non-integer relationship to the VCO1 frequency. |
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XO_N | 32 | I | ||||||
OUTPUT BLOCKS | ||||||||
OUT0_P | 14 | O | Clock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL and HCSL. Unused differential outputs should be terminated if active or left floating if disabled through registers. The OUT[0:3] bank is preferred for PLL1 clocks to minimize output crosstalk. |
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OUT0_N | 15 | O | ||||||
OUT1_P | 17 | O | ||||||
OUT1_N | 16 | O | ||||||
OUT2_P | 20 | O | ||||||
OUT2_N | 21 | O | ||||||
OUT3_P | 23 | O | ||||||
OUT3_N | 22 | O | ||||||
OUT4_P | 39 | O | Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if active or left floating if disabled through registers. The OUT[4:7] bank is preferred for PLL2 clocks to minimize output crosstalk. When PLL2 is not used, the OUT[4:7] bank can be used for PLL1 clocks without risk of cross-coupling from PLL2. |
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OUT4_N | 38 | O | ||||||
OUT5_P | 42 | O | ||||||
OUT5_N | 41 | O | ||||||
OUT6_P | 45 | O | ||||||
OUT6_N | 44 | O | ||||||
OUT7_P | 48 | O | ||||||
OUT7_N | 47 | O | ||||||
LOGIC CONTROL / STATUS (2)(3) | ||||||||
HW_SW_CTRL | 9 | I | Device Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions. The input level is sampled only at device power-on reset (POR). See Table 1 for start-up mode descriptions and logic pin functions. |
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PDN | 13 | I | Device Power-Down (active low).
When PDN is pulled low, the device is in hard-reset and all blocks including the serial interface are powered down. When PDN is pulled high, the device is started according to device mode selected by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state. |
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SDA/SDI | 25 | I/O | I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 1.
When HW_SW_CTRL is 0 or 1, the serial interface is I2C. SDA and SCL pins (open drain) require external I2C pullup resistors. The default 7-bit I2C address is 11001xxb, where the MSB bits (11001b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO1 input state (3-level) during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b. When HW_SW_CTRL is Float, the serial interface is SPI (4-wire, Mode 0) using the SDI, SCK, SCS, and SDO pins. |
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SCL/SCK | 26 | I | I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 1. | |||||
GPIO0/SYNCN | 12 | I | Multifunction Inputs or Outputs.
See Table 1. |
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GPIO1/SCS | 24 | I | ||||||
GPIO2/SDO/
FINC |
30 | I/O | ||||||
STATUS0 | 1 | I/O | Status Outputs 0 and 1.
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain), and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused. In I2C mode, the STATUS1/FDEC pin can function as a DCO mode control input pin. See Table 1. |
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STATUS1/
FDEC |
2 | I/O | ||||||
REFSEL | 8 | I | Manual DPLL Reference Clock Input Selection. (3-level, 1.8-V compatible).
REFSEL = 0 (PRIREF), 1 (SECREF), or Float or VIM (Auto Select). This control pin must be enabled by register default or programming. Leave pin floating if unused. |