SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 55 shows the general sequence for PLL start-up after device configuration. This sequence is also applicable after a device soft-reset or individual PLL soft-reset. To ensure proper VCO calibration, it is critical for the external XO clock to be stable in amplitude and frequency prior to the start of VCO calibration. Otherwise, the VCO calibration can fail and prevent start-up of the PLL and its output clocks.