SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The reference inputs (PRIREF and SECREF) can accept differential or single-ended clocks. Each input has programmable input type, termination, and AC-coupled input biasing configurations as shown in Figure 28. Each input buffer drives the reference input mux of the DPLL block. The DPLL input mux can select from any of the reference inputs. The DPLL can switch between inputs with different frequencies provided they can be divided-down to a common frequency by DPLL R dividers. The reference input paths also drive the various detector blocks for reference input monitoring and validation.
Table 3 lists the reference input buffer configurations for common clock interface types.
REFx_TYPE | INPUT TYPES | INTERNAL SWITCH SETTINGS | ||
---|---|---|---|---|
INTERNAL TERM.
(S1, S2)(1) |
INTERNAL BIAS
(S3)(2) |
LVCMOS SLEW RATE DETECT (S4)(3) | ||
0h | LVDS, CML, LVPECL
(DC-coupled) |
OFF | OFF | OFF |
1h | LVDS, CML, LVPECL
(AC-coupled) |
OFF | ON (1.3 V) | OFF |
3h | LVDS, CML, LVPECL
(AC-coupled, internal 100-Ω) |
100 Ω | ON (1.3 V) | OFF |
4h | HCSL
(DC-coupled, internal 50-Ω) |
50 Ω | OFF | OFF |
8h | LVCMOS
(DC-coupled) |
OFF | OFF | ON |
Ch | Single-ended
(DC-coupled, internal 50-Ω) |
50 Ω | OFF | ON |