SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The device supports a SPI block write and block read transfers. A SPI block transfer is exactly (2 + N) bytes long, where N is the number of data bytes to write or read. The host device (SPI master) is only required to specify the lowest address of the sequence of addresses to be accessed. The device will automatically increment the internal register address pointer if the SCS pin remains low after the host finishes the initial 24-bit transmission sequence. Each transfer of eight bits (a data payload width) results in the device automatically incrementing the address pointer (provided the SCS pin remains active low for all sequences).