SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The DPLL supports a zero-delay mode (ZDM) synchronization option to achieve a known and deterministic phase relationship between the selected DPLL reference input and the OUT7 clock. This is primarily intended to achieve phase alignment between a 1-PPS input and 1-PPS output. See Zero-Delay Mode (ZDM) Synchronization for 1-PPS Input and Output.