SNAS859 March   2024 LMK05318B-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Device Start-Up Modes
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 5.5 Thermal Information: 10-Layer Custom PCB
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL Mode
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO_P/N)
      2. 7.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With 1-PPS Inputs
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Amplitude Monitor
          3. 7.3.7.2.3 Frequency Monitoring
          4. 7.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 7.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 7.3.7.2.6 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 7.3.8.3.3 APLL2 Reference (R) Dividers
        4. 7.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.8.5  APLL Feedback Divider Paths
          1. 7.3.8.5.1 APLL1 N Divider With SDM
          2. 7.3.8.5.2 APLL2 N Divider With SDM
        6. 7.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 7.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 7.3.8.7.1 VCO Calibration
        8. 7.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 7.3.8.9  DPLL Reference (R) Divider Paths
        10. 7.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 7.3.8.11 DPLL Loop Filter (DLF)
        12. 7.3.8.12 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Channel Muxes
      11. 7.3.11 Output Dividers (OD)
      12. 7.3.12 Clock Outputs (OUTx_P/N)
        1. 7.3.12.1 AC-Differential Output (AC-DIFF)
        2. 7.3.12.2 HCSL Output
        3. 7.3.12.3 1.8V LVCMOS Output
        4. 7.3.12.4 Output Auto-Mute During LOL
      13. 7.3.13 Glitchless Output Clock Start-Up
      14. 7.3.14 Clock Output Interfacing and Termination
      15. 7.3.15 Output Synchronization (SYNC)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up Modes
        1. 7.4.1.1 EEPROM Mode
      2. 7.4.2 PLL Operating Modes
        1. 7.4.2.1 Free-Run Mode
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 Locked Mode
        4. 7.4.2.4 Holdover Mode
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 7.4.4.1 DCO Frequency Step Size
        2. 7.4.4.2 DCO Direct-Write Mode
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Communication
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Communication
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map and EEPROM Map Generation
      5. 7.5.5 General Register Programming Sequence
      6. 7.5.6 EEPROM Programming Flow
        1. 7.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 7.5.6.1.1 Write SRAM Using Register Commit
          2. 7.5.6.1.2 Program EEPROM
        2. 7.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 7.5.6.2.1 Write SRAM Using Direct Writes
          2. 7.5.6.2.2 User-Programmable Fields In EEPROM
      7. 7.5.7 Read SRAM
      8. 7.5.8 Read EEPROM
      9. 7.5.9 EEPROM Start-Up Mode Default Configuration
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PDN) Pin
      3. 8.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.3.1 Mixing Supplies
        2. 8.1.3.2 Power-On Reset (POR) Circuit
        3. 8.1.3.3 Powering Up From a Single-Supply Rail
        4. 8.1.3.4 Power Up From Split-Supply Rails
        5. 8.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 8.1.4 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
      2. 8.4.2 Device Current and Power Consumption
        1. 8.4.2.1 Current Consumption Calculations
        2. 8.4.2.2 Power Consumption Calculations
        3. 8.4.2.3 Example
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
        1. 8.5.3.1 Support for PCB Temperature up to 105°C
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 RGZ Package48-Pin VQFNTop View
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
POWER
GNDPADGGround / Thermal Pad.
Connect the exposed pad to the to PCB ground for proper electrical and thermal performance. A 5×5 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
VDD_IN5PCore Supply (3.3V) for Primary and Secondary Reference Inputs.
Place a nearby 0.1µF bypass capacitor on each pin.
VDD_XO33PCore Supply (3.3V) for XO Input.
Place a nearby 0.1µF bypass capacitor on each pin.
VDD_PLL127PCore Supply (3.3V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1µF bypass capacitor on each pin.
VDD_PLL236P
VDD_DIG4P
VDDO_0118POutput Supply (1.8, 2.5, or 3.3V) for Clock Outputs 0 to 7.
Place a nearby 0.1µF bypass capacitor on each pin. Can be left floating or No Connect if the corresponding output is unused. Output supply voltage level can be mixed or the same across VDDO_x pins. Refer to Mixing Supplies.
VDDO_2319P
VDDO_437P
VDDO_540P
VDDO_643P
VDDO_746P
CORE BLOCKS
LF129AExternal Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby capacitor on each pin. For LF1, a 0.47µF capacitor is suggested for typical APLL1 loop bandwidths around 1.0kHz. For LF2, a 0.1µF capacitor is suggested for typical APLL2 loop bandwidth around 500kHz.
LF234A
CAP_PLL128AExternal Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10µF bypass capacitor on each pin.
CAP_PLL235A
CAP_DIG3A
INPUT BLOCKS
PRIREF_P6IDPLL Primary and Secondary Reference Clock Inputs.
Each input pair can accept a differential or single-ended clock as a reference to the DPLL. Each pair has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down to ground. An unused input pair can be left floating.

For low-frequency input (< 2kHz), disable the internal AC-coupling capacitor to improve noise immunity. Differential Input and LVCMOS input can be DC-coupled to the receiver.


Programmable input types are detailed in Reference Inputs (PRIREF_P/N and SECREF_P/N).
PRIREF_N7I
SECREF_P10I
SECREF_N11I
XO_P31IXO/TCXO/OCXO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator as a reference to the APLLs. This input has a programmable input type with internal termination to support AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5V) can be applied to the P input with the N input pulled down to ground. A low-frequency TCXO or OCXO can be used to set the clock output frequency accuracy and stability during free-run and holdover modes.

In DPLL mode, the XO frequency must have a non-integer relationship to the VCO1 frequency so APLL1 can operate in fractional mode (required for proper DPLL operation). In APLL-only (free-run) mode, the XO frequency can have either an integer or non-integer relationship to the VCO1 frequency.
Programmable input types and frequency options are detailed in Oscillator Input (XO_P/N).
XO_N32I
OUTPUT BLOCKS
OUT0_P14OClock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, and HCSL.
Unused differential outputs must be terminated if active or disabled through registers if left floating.
The OUT[0:3] bank is preferred for PLL1 clocks to minimize output crosstalk.
OUT0_N15O
OUT1_P17O
OUT1_N16O
OUT2_P20O
OUT2_N21O
OUT3_P23O
OUT3_N22O
OUT4_P39OClock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or 1.8V LVCMOS clocks (one or two per pair).
Unused differential outputs must be terminated if active or disabled through registers if left floating.
The OUT[4:7] bank is preferred for PLL2 clocks to minimize output crosstalk. When PLL2 is not used, the OUT[4:7] bank can be used for PLL1 clocks without risk of cross-coupling from PLL2.
OUT4_N38O
OUT5_P42O
OUT5_N41O
OUT6_P45O
OUT6_N44O
OUT7_P48O
OUT7_N47O
LOGIC CONTROL / STATUS (2)(3)
HW_SW_CTRL9IDevice Start-Up Mode Select (3-level, 1.8V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the registers, serial interface, and logic pin functions. The input level is sampled only at device power-on reset (POR).
See Table 4-2 for start-up mode descriptions and logic pin functions.
PDN13IDevice Power-Down (active low).
When PDN is pulled low, the device is in hard-reset and all blocks including the serial interface are powered down. When PDN is pulled high, the device is started according to device mode selected by HW_SW_CTRL and begins normal operation with all internal circuits reset to the initial state.
SDA/SDI25I/OI2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 4-2.
When HW_SW_CTRL is 0 or 1, the serial interface is I2C. SDA and SCL pins (open-drain) require external I2C pullup resistors. The default 7-bit I2C address is 11001xxb, where the MSB bits (11001b) are initialized from on-chip EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0, the LSBs are determined by the GPIO1 input state (3-level) during POR. When HW_SW_CTRL is 1, the LSBs are fixed to 00b.
When HW_SW_CTRL is Float, the serial interface is SPI (4-wire, Mode 0) using the SDI, SCK, SCS, and SDO pins.
SCL/SCK26II2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 4-2.
GPIO0/SYNCN12IMultifunction Inputs or Outputs.
See Table 4-2.
GPIO1/SCS24I
GPIO2/SDO/
FINC		30I/O
STATUS01I/OStatus Outputs 0 and 1.
Each output has programmable status signal selection, driver type (3.3V LVCMOS or open-drain), and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
In I2C mode, the STATUS1/FDEC pin can function as a DCO mode control input pin. See Table 4-2.
STATUS1/
FDEC		2I/O
REFSEL8IManual DPLL Reference Clock Input Selection. (3-level, 1.8V compatible).
REFSEL = 0 (PRIREF), 1 (SECREF), or Float or VIM (Auto Select). This control pin must be enabled by register default or programming. Leave pin floating if unused.
(1) G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
(2) Internal resistors: PDN pin has 200kΩ pullup to VDD_IN. HW_SW_CTRL, GPIO, REFSEL, and STATUS pins each have a 150kΩ bias to VIM (approximately 0.8V) when PDN = 0 or 400kΩ pulldown when PDN = 1.
(3) Unless otherwise noted: Logic inputs are 2-level, 1.8V compatible inputs. Logic outputs are 3.3V LVCMOS levels.